LA73033M
No.A0646-17/24
Device address
Gr address
bit7 (MSB)
bit6
bit5
bit4
bit3
bit2
bit1
bit0 (LSB)
SW1
00000001
INSEL3
INSEL2
INSEL1
LPF
SWGAIN1
SWGAIN2
YOUT SEL
*Res
SW2
00000010
AGC
V.SYNC
*Res
*Res
CLPOFF1
CLPIUP
TEST2
TEST1
DR1
00000011
SCART
YC MIX
CDC2
CDC1
PROG
GB MUTE
YC MUTE
CP MUTE
DR2
00000100
CV/ S GAIN
CP GAIN
CV/ S DRIVE
CP DRIVE
SCART YC
*Res
*Res
CLPOFF2
* Res means a reserved bit.
Initial state
SW block
INSEL3
INSEL2
INSEL1
Input selection
Mode
0
0
0
IN1
Component
0
0
1
IN1
RGB
0
1
0
IN2
Composite/ S
0
1
1
IN3
Composite/ S
1
0
0
IN4
Composite/ S
1
0
1
IN5
Composite/ S
1
1
0
IN6
Composite/ S
INSEL3
INSEL2
INSEL1
SW block input selection/mode
changeover
1
1
1
Prohibition
LPF
SW block LPF
1 : LPF on
0 : LPF off
SWGAIN1
SW block amplifier gain changeover 1 (for composite/ Y
signal)
SW block amplifier gain changeover 2 (C/ component/
RGB signal)
SW block YOUT output selection
1 : +6dB (AGC used+3dB)
0 : 0dB
SWGAIN2
1 : +6dB (AGC used+3dB)
0 : 0dB
YOUT SEL
1 : Composite
0 : Y
AGC
SW block AGC ON/OFF
1 : ON
0 : OFF
V.SYNC
SYNC output changeover
1 : V-SYNC output
0 : C- SYNC output (for detection of weak
field)
0 : Clamp ON
CLPOFF1
Test mode (SW block input clamp OFF)
1 : Clamp OFF
CLPIUP
Increase in SW block clamp current
1 : Increase in the clamp
current
00 : C-SYNC (Normal)
0 : Clamp current normal
TEST2
01 : Clamp pulse
TEST1
C-SYNC output (TEST mode)
10 : Prohibition
11 : Macro vision gate
Driver block
SCART
Driver block component mode changeover
1 : SCART (RGB)
0 : Y/ Cb/ Cr
YC MIX
Driver block composite output selection
1 : Y/ C MIX
0 : Composite (Y/ C MIX OFF)
CDC2
00 : Low (0V) 4 : 3mode
01 : Middle (2.2V) letter box
CDC1
Driver block C_DC output voltage
10 : High (5V) squeeze
11 : Prohibition
PROG
Driver block LPF changeover
1 : Progressive
0 : Interlace
GB MUTE
Driver block G/B MUTE
1 : MUTE ON
0 : MUTE OFF
YC MUTE
Driver block YC MUTE
1 : MUTE ON
0 : MUTE OFF
CP MUTE
Driver block component MUTE
1 : MUTE ON
0 : MUTE OFF
CV/ S GAIN
Driver block composite/ S amplifier gain
1 : +9dB
0 : +6dB
CP GAIN
Driver block component amplifier gain
1 : +9dB
0 : +6dB
CV/ S DRIVE
Driver block composite/ S output drive capacity
1 : Two-system drive
0 : One-system drive
CP DRIVE
Driver block component output drive capacity
1 : Two-system drive
0 : One-system drive
SCART YC
Driver block SCART YC mode changeover
1 : YC
0 : RGB
CLPOFF2
Test mode (driver block input clamp OFF)
1 : Clamp OFF
0 : Clamp ON
*Initial setting at power ON
Gr address
data
SW1
00000001
01100010
SW2
00000010
00000000
DR1
00000011
01000000
DR2
00000100
00110000