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參數(shù)資料
| 型號(hào)： | LA72730-N-E |
| 廠商： | ON Semiconductor |
| 文件頁(yè)數(shù)： | 3/8頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC AUDIO/VIDEO SWITCH TV 24SDIP |
| 標(biāo)準(zhǔn)包裝： | 22 |
| 功能： | 音頻/視頻切換 |
| 電路： | 1 X 4:1（增強(qiáng)監(jiān)控器） |
| 電壓電源： | 單電源 |
| 電壓 - 電源，單路/雙路(±)： | 4.5 V ~ 5.5 V |
| 工作溫度： | -20°C ~ 70°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 24-SDIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 24-SDIP |
| 包裝： | 管件 |
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
MOS INTEGRATED CIRCUIT
μPD720102
USB 2.0 HOST CONTROLLER
Document No.
S17998EJ4V0DS00 (4th edition)
Date Published March 2007 NS CP (N)
Printed in Japan
DATA SHEET
2006
The mark "<R>" shows major revised points.
The
μPD720102 complies with the universal serial bus specification revision 2.0 and open host controller interface
specification for full-/low-speed signaling and Intel's enhanced host controller interface specification for high-speed
signaling and works up to 480 Mbps. The
μPD720102 is integrated 2 host controller cores with PCI interface and USB
2.0 transceivers into a single chip.
Detailed function descriptions are provided in the following user’s manual. Be sure to read the manual before designing.
μPD720102 User’s Manual: S17999E
FEATURES
Compliant with universal serial bus specification revision 2.0 (data rate: 1.5/12/480 Mbps)
Compliant with open host controller interface specification for USB release 1.0a
Compliant with enhanced host controller interface specification for USB revision 1.0
PCI multi-function device consists of one OHCI host controller core for full-/low-speed signaling and one EHCI host
controller core for high-speed signaling
Root hub with 3 (Max.) downstream facing ports which are shared by OHCI and EHCI host controller cores
All downstream facing ports can handle high-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps)
transaction
Supports hyper-speed transfer mode using HSMODE signal
32-bit 33 MHz host interface compliant with PCI specification revision 2.2
Supports PCI mobile design guide version 1.1
Supports PCI-bus power management interface specification revision 1.1
PCI bus bus-master access
Supports 3.3 V PCI
System clock is generated by 30 MHz crystal or 48 MHz clock input
Operational registers direct-mapped to PCI memory space
3.3 V single power supply, 1.5 V internal operating voltage from on chip regulator
On chip Rs and Rpd resistors for USB signals
ORDERING INFORMATION
Part Number
Package
Remark
μPD720102GC-YEB-A
120-pin plastic TQFP (fine pitch) (14
× 14)
Lead-free product
μPD720102F1-CA7-A
121-pin plastic FBGA (8
× 8)
Lead-free product
<R>
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