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參數(shù)資料
| 型號： | LA70100M |
| 廠商： | SANYO SEMICONDUCTOR CO LTD |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO30 |
| 封裝： | 0.375 INCH, MFP-30 |
| 文件頁數(shù)： | 15/16頁 |
| 文件大?。?/td> | 279K |
| 代理商： | LA70100M |
LA70100M
No.7204-8/16
(3) CLK INPUT, AFC
Input a frequency of 4.433619MHz sine wave or rectangle waveform signal of PAL fsc to CLK input terminal. This signal is
used for automatically adjusting the BELL filter and generating timing pulse for AFC and for sync gate. AFC circuit
automatically adjusts the frequency characteristics for each BPF.
(4) SYNC GATE CIRCUIT
Vertical sync signal is extracted by a synchronous separate circuit from Composite Sync signal that has been input from Pin
29, and is conducted to BELL/A-BELL filter automatic adjusting circuit. Additionally, SYNC GATE pulse and sample hold
pulse are generated by the logic circuit.
(5) BGP generator circuit
BGP is used for killer circuit in REC Mode, AGC circuit in PB Mode, and SECAM discrimination circuit.
In BP Mode, AGC circuit detects the scale of the signal of BGP duration (ID) so that the output of 4 times multiplier circuit be
constant. In SECAM discrimination circuit, BGP is used for making the S/H pulse (SP9, SP2 in Figure 9) mentioned later.
Controlling Pin 4 can convert the timing for Composite Sync that is input to Pin 27. The width of BGP is determined by the
constant of the inside of IC to about 2.5
s. And BGP timing can be monitored by Pin 28 in test mode (Pin 9 voltage = 5V).
for BELL ADJUST CLOCK
4.43MHz
VCO
AFC
BUFF
2
4.43MHz
CLOCK
for EACH FILTER ADJUST
3
Fig.3
29
SYNC
SEPA
Composite sync
CONTROL
LOGIC
4.43MHz
CLOCK
C.SYNC
V.SYNC
BELL ADJUST
SECAM DET SAMPLE HOLD-3
SYNC GATE/MUTE
SECAM DET SAMPLE HOLD-1, 2
C.sync
V-MUTE
BELL ADJUST
GATE
Fig.4
C.sync
SYNC GATE
MUTE
700s
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