參數資料
型號: L9230
廠商: 意法半導體
英文描述: SPI CONTROLLED H-BRIDGE
中文描述: 可控的SPI H橋
文件頁數: 10/25頁
文件大?。?/td> 218K
代理商: L9230
L9230
10/25
t
v
Data Valid CL = 40pF
Data Valid CL = 200pF
(referred to L9230)
40
150
ns
ns
t
su
Data Setup Time
(referred to master)
50
ns
t
h
Data Hold Time
(referred to master)
20
ns
t
dis
Disable Time
(referred to L9230)
100
ns
t
dt
Transfer Delay
(referred to master)
150
ns
t
SCKH
Serial clock high time
(referred to master)
50
μ
s
t
SCKL
Access time
(referred to master)
8.35
ns
Clock inactive before
chipselect becomes valid
200
ns
Clock inactive after
chipselect becomes valid
200
ns
t
rs
rise-, fall time
Load on SO 50pF
20
ns
DIAGNOSTIC
Diagnostic Threshold
(Open Load Detection DMS > 4,5V, EN < 0,8V)
V
OUT1
V
OUT2
Load is available
0.8
0.8
V
V
V
OUT1
V
OUT2
Load is missing
1
V
S
0.8
V
V
I
OUT2
-I
OUT1
Diagnostic Current
DMS > 4.5V, EN < 0.8V
DMS > 4.5V, EN < 0.8V
700
1000
1000
1500
1300
2000
μ
A
μ
A
Tracking Diagnostic Current
I
OUT1
/ I
OUT2
1.4
1.5
1.6
t
D
Delay Time
30
100
ms
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
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