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參數(shù)資料
| 型號： | L7203S |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | SMOOTH DRIVE SPINDLE MOTOR FOR OPTICAL DRIVE APPLICATION WITH POWER INTEGRATED |
| 中文描述： | 傳動平穩(wěn)主軸馬達驅(qū)動功率集成應(yīng)用光學(xué) |
| 文件頁數(shù)： | 7/13頁 |
| 文件大小： | 170K |
| 代理商： | L7203S |
Fscan has a frequency 36 times of (1/T). The
Fscan is generated from the Zero-cross fre-
quency measured at the previous cycle.
So, if the motor speed changes, the zero-cross is
not constant, the Frequency Multiplier adjusts the
scan clock, ensuring the synchronization between
the Zero-Cross signal and the sinusoidal output
voltage.
Memory and Memory Scan
The memory stores 3x36 samples describing 3
signals. As each sample is represented in a byte,
it may have a value in the range 0 to 255.
The shape of these three signals are designed in
order to generate three sinusoidal voltages
across the Motor coils ensuring the highest per-
formances in term of power losses and motor
speed. The shape of the signals are reported in
fig. 7.
In Fig 8 is swown the "differential" voltage across
the motor coil U and the motor coil V. Obviously,
the voltage shape across the motor coil U and W
and the voltage across the motor coil V and W
are also sinusoidal and dephased of 120 and 240
degrees respect the voltage shown in fig. 8.
The Memory and Memory scan block receives
the scan clock, and at each clock provides the
sample addressed by an internal address regis-
ter.
This register is initialized with the memory ad-
dress of the wave sample synchronized with the
Zero-Cross signal. The maximum efficiency (i.e.
the maximum motor speed for a particular value
of current) for the motor driving may be reached
ensuring a particular value PH of dephase be-
tween the Zero-Cross signal and the voltage out-
put signal.
This value is written by the external controller us-
ing PHS pin (see Phase Shift Block section).
Kval Block and PWM interface
This unit contains a register storing the Kval
value. The Kval value represents a multiplying
factor to modulate the 3 profile signals amplitude
and it is generated starting from the PWMIN sig-
nal coming from the external system controller.
The Kval block receives the PWMIN signals and
calculates the Kval value through the reference
triangular signal.
This signal is generated by a 10 bit counter that
starts counting from 1023 to 0 at Fsys rate, and
then restart up to 1023. The resolution is
±
1LSB.
Internal triangular wave is synchronized with the
PWMIN falling edge.
The PWMIN signal contains information regard-
ing both the amplitude and to the sign of the con-
trol variable. If the duty cycle is less than 50% the
Kval is in the range (-1023, -1), while if the duty
cycle is equal or greater than 50% the kval is in
the range (0, 1023).
A negative Kval value (i.e. PWM duty cycle from
0 to 50%) indicates an active brake and gener-
ates a 180 degree shift in the voltage profile
scan.
The rising edge of the PWMIN signal determines
the kval on the reference triangular waveform.
If the PWMIN signal is stable during the entire cy-
cle, the Kval is evaluated according to the follow-
ing rule:
- PWMIN signal stable to 1 -> Kval = +1023
- PWMIN signal stable to 0 -> Kval = -1023
In order to ensure the synchronization between
INTERNAL
REFERENCE
SIGNAL
PWMIN
0
1023
KVAL < 0
KVAL > 0
KVAL < 0
D98IN884
Figure 9.
U-W
D98IN931
Figure 8.
V
U
W
D98IN930
Figure 7.
L7203
7/13
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| L7204 | 功能描述:重負荷電源連接器 PLUG-YC-#2/0-PC RoHS:否 制造商:Hirose Connector 系列:PS2 產(chǎn)品類型:Connectors 位置/觸點數(shù)量: 端接類型:Crimp 觸點材料: 觸點電鍍:Gold 電壓額定值: 電流額定值:300 A 附件類型: |
| L7204A | 制造商:Agilent Technologies 功能描述:L7204A / Switch, SP4T, DC-4 GHz, unterminated, 24VDC (L-SERIES) |
| L7204B | 制造商:Agilent Technologies 功能描述:L7204B / Switch, SP4T, DC-20 GHz, unterminated, 24VDC (L-SERIES) |
| L7204C | 制造商:Agilent Technologies 功能描述:L7204C / Switch, SP4T, DC-26.5 GHz, unterminated, 24VDC (L-SERIES) |
| L7204G1 | 功能描述:重負荷電源連接器 PLUG-YC-#1/0-PC RoHS:否 制造商:Hirose Connector 系列:PS2 產(chǎn)品類型:Connectors 位置/觸點數(shù)量: 端接類型:Crimp 觸點材料: 觸點電鍍:Gold 電壓額定值: 電流額定值:300 A 附件類型: |
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