參數(shù)資料
型號(hào)： L6731B
廠商： STMICROELECTRONICS
元件分類： 穩(wěn)壓器
英文描述： 20 A SWITCHING CONTROLLER, 500 kHz SWITCHING FREQ-MAX, PDSO16
封裝： HTSSOP-16
文件頁(yè)數(shù)： 21/24頁(yè)
文件大?。?/td> 439K
代理商： L6731B
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Pin connections and functions
L6731B
6/24
3
Pin connections and functions
Figure 2.
Pins connection ( Top view)
Table 3.
Pin functions
Pin n.
Name
Function
1
PGOOD
This pin is an open collector output and it is pulled low if the output voltage is not
within the specified thresholds (90%-110%). If not used it may be left floating. Pull-up
this pin to VCCDR with a 10K resistor to obtain a logical signal.
2
VTTREF
This pin is connected to the output of an internal buffer that provides of DDR-IN.
This pin can be connected to the VTTREF input of the DDR memory itself. Filter to GND
with 10nF capacitor.
3
SGND
All the internal references are referred to this pin.
4
FB
This pin is connected to the error amplifier inverting input. Connect it to VOUT through
the compensation network. This pin is also used to sense the output voltage in order
to manage the over voltage conditions and the PGood signal.
5
COMP
This pin is connected to the error amplifier output and is used to compensate the
voltage control feedback loop.
6
SS/INH
The soft-start time is programmed connecting an external capacitor from this pin and
GND. The internal current generator forces a current of 10
A through the capacitor.
When the voltage at this pin is lower than 0.5V the device is disabled.
7
DDR-IN
By setting the voltage at this pin is possible to select the internal/external reference
and the switching frequency:
VEAREF 0-80% of VCCDR -> External Reference/FSW=250KHz
VEAREF = 80%-95% of VCCDR -> VREF = 0.6V/FSW=500KHz
VEAREF = 95%-100% of VCCDR -> VREF = 0.6V/FSW=250KHz
An internal clamp limits the maximum VEAREF at 2.5V (typ.). The device captures the
analog value present at this pin at the start-up when VCC meets the UVLO threshold.
1
2
3
4
5
6
11
12
HTSSOP16
13
14
15
16
SGND
DDR-IN
FB
PGOOD
VTTREF
COMP
VCC
LGATE
PHASE
SS/INH
PGND
7
10
VCCDR
BOOT
HGATE
8
9
OCL
OCH
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