參數(shù)資料
型號(hào): L6728
廠商: 意法半導(dǎo)體
英文描述: Single phase PWM controller with PowerGOOD
中文描述: 單相PWM控制器與電源良好
文件頁數(shù): 14/32頁
文件大小: 942K
代理商: L6728
Output voltage setting and protections
L6728
14/32
9
Output voltage setting and protections
L6728 is capable to precisely regulate an output voltage as low as 0.8V. In fact, the device
comes with a fixed 0.8V internal reference that guarantee the output regulated voltage to be
within ±0.8% tolerance over line and temperature variations (excluding output resistor
divider tolerance, when present).
Output voltage higher than 0.8V can be easily achieved by adding a resistor R
OS
between
FB pin and ground. Referring to
Figure 1
, the steady state DC output voltage will be:
where V
REF
is 0.8V.
L6728 monitors the voltage at VSEN pin and compares it to internal reference voltage in
order to provide Under Voltage and Over Voltage protections as well as PGOOD signal.
According to the level of VSEN, different actions are performed from the controller:
PGOOD
If the voltage monitored through VSEN exits from the PGOOD window limits, the device
de-asserts the PGOOD signal still continuing switching and regulating. PGOOD is
asserted at the end of the soft-start phase.
Under Voltage Protection
If the voltage at VSEN pin drops below UV threshold, the device turns off both HS and
LS MOSFETs, latching the condition. Cycle VCC to recover.
Over Voltage Protection
If the voltage at VSEN pin rises over OV threshold (1V typ), over voltage protection
turns off HS MOSFET and turns on LS MOSFET. The LS MOSFET will be turned off as
soon as VSEN goes below Vref/2 (0.4V). The condition is latched, cycle VCC to
recover. Notice that, even if the device is latched, the device still controls the LS
MOSFET and can switch it on whenever VSEN rises above 0.4V.
Feedback Disconnection Protection
In order to provide load protection even if VSEN pin is not connected, a 100nA bias
current is always sourced from this pin. If VSEN pin is not connected, this current will
permanently pull it up causing the device to detect an OV: thus LS will be latched on
preventing output voltage from rising out of control.
V
OUT
V
REF
1
R
R
OS
----------
+
=
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