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參數(shù)資料
| 型號： | L6722TR |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | SWITCHING CONTROLLER, 300 kHz SWITCHING FREQ-MAX, QCC36 |
| 封裝： | 6 X 6 MM, 1 MM PITCH, VFQFPN-36 |
| 文件頁數(shù)： | 8/34頁 |
| 文件大?。?/td> | 421K |
| 代理商： | L6722TR |
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6 Current sharing loop and current reading
L6722
16/34
6
Current sharing loop and current reading
L6722 embeds two separate Current-Reading circuitries used to perform Current-Sharing and
OCP through ISENx pins and Voltage-Positioning through CS+ and CS- pins (See Section 7).
Current-sharing control-loop and connections are reported in Figure 6: the current read through
the ISENx pins is converted into a current IINFOx proportional to the current delivered by each
phase and the information about the average current IAVG = ΣIINFOx / 3 is internally built into the
device. The error between the read current IINFOx and the reference IAVG is then converted into
a voltage that with a proper gain is used to adjust the duty cycle whose dominant value is set by
the voltage error amplifier in order to equalize the current carried by each phase.
The current flowing trough each phase is read using the voltage drop across the low-side
mosfets RdsON or across a sense resistor in its series and it is internally converted into a
current. The trans-conductance ratio is issued by the external resistor RISEN placed outside the
chip between ISENx and the reading point (usually the LS mosfet Drain).
The current sense circuit tracks the current information for a time TTRACK centered in the
middle of the LS conduction time and holds the tracked information during the rest of the
period. The current that flows from the ISENx pin is the current information used by the device to
perform current sharing and OCP and it is given by:
where RdsON is the ON resistance of the low side mosfet and RISEN is the trans-conductance
resistor connected between the ISENx pins and the LS Drain; IPHASEx is the current carried by
the relative phase and IINFOx is the current information signal reproduced internally.
Caution:
Asymmetries in the RISENx values are allowed in order to create intentional current-unbalance
so that one phase can carry higher currents or support different cooling. To increase the current
in any of the phases, the value of the related RISEN can be slightly increased starting from the
theoretical value extracted from the above reported relationships. Start from the coolest phase
first to get the thermal balance.
Figure 6.
Current sharing loop and current reading connections
I
ISENx
R
dsON
R
ISEN
-----------------
I
PHASEx
I
INFOx
==
I
INFO1
PWM1 Out
From EA
I
INFO2
I
AVG
PWM2 Out
I
INFO3
PWM3 Out
AVG
ISENx
LGATEx
I
PHASEx
R
ISEN
IISENx
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