參數(shù)資料
型號: L6713ATR
廠商: STMICROELECTRONICS
元件分類: 穩(wěn)壓器
英文描述: 2 A SWITCHING CONTROLLER, 225 kHz SWITCHING FREQ-MAX, PQFP64
封裝: 10 X 10 MM, TQFP-64
文件頁數(shù): 64/64頁
文件大小: 801K
代理商: L6713ATR
L6713A
Pin settings
9/64
30
CS1+
Channel 1 current sense positive input.
Connect through an R-C filter to the phase-side of the channel 1 inductor.
See “Layout guidelines” Section for proper layout of this connection.
31
CS1-
Channel 1 current sense negative input.
Connect through a Rg resistor to the output-side of the channel 1 inductor.
See “Layout guidelines” Section for proper layout of this connection.
32
SS/ LTBG/
AMD
Soft-start oscillator, LTB gain and AMD selection pin.
It allows selecting between INTEL DACs and AMD DAC.
Short to SGND to select AMD DAC otherwise INTEL mode is selected.
When INTEL mode is selected trough this pin it is possible to select the soft-
start time and also the gain of LTB Technology. See “Soft-start” Sectionand
33
OVP
Over voltage programming pin. Internally pulled up by 12.5 A (typ) to 5 V.
Leave floating to use built-in protection thresholds as reported into Table 12.
Connect to SGND through a ROVP resistor and filter with 100 pF (max) to set
the OVP threshold to a fixed voltage according to the ROVP resistor.
34
VID_SEL
Intel mode. Internally pulled up by 12.5 A (typ) to 5 V.
It allows selecting between VR10 (short to SGND, Table 8) or VR11 (floating,
AMD mode. Not applicable. Needs to be shorted to SGND.
35
OCSET
Over current set pin.
Connect to SGND through a ROCSET resistor to set the OCP threshold. Connect
also a COCSET capacitor to set a delay for the OCP intervention.
36
FBG
Connect to the negative side of the load to perform remote sense.
See “Layout guidelines” Section for proper layout of this connection.
37
OSC/
FAULT
Oscillator pin.
It allows programming the switching frequency FSW of each channel: the
equivalent switching frequency at the load side results in being multiplied by the
phase number N.
Frequency is programmed according to the resistor connected from the pin vs.
SGND or VCC with a gain of 8 kHz/A (see relevant section for details).
Leaving the pin floating programs a switching frequency of 200kHz per phase.
The pin is forced high (5 V) to signal an OVP FAULT: to recover from this
condition, cycle VCC or the OUTEN pin. See “Oscillator” Section for details.
38
VID7/DVID
VID7 - Intel mode. See VID5 to VID0 section.
DVID - AMD mode. DVID output.
CMOS output pulled high when the controller is performing a D-VID transition
(with 32 clock cycle delay after the transition has finished). See “Dynamic VID
transitions” Section Section for details.
39
VID6
Intel mode. See VID5 to VID0 section.
AMD mode. Not applicable. Needs to be shorted to SGND.
Table 2.
Pin description (continued)
Pin
Function
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