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參數(shù)資料
| 型號(hào)： | L6712QTR |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | TWO-PHASE INTERLEAVED DC/DC CONTROLLER |
| 中文描述： | 兩相交錯(cuò)DC / DC控制器 |
| 文件頁數(shù)： | 10/27頁 |
| 文件大?。?/td> | 1074K |
| 代理商： | L6712QTR |
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L6712A L6712
10/27
(with external reference)
DRIVER SECTION
The integrated high-current drivers allow using different types of power MOS (also multiple MOS to reduce
the R
dsON
), maintaining fast switching transition.
The drivers for the high-side mosfets use BOOTx pins for supply and PHASEx pins for return. The drivers
for the low-side mosfets use VCCDR pin for supply and PGND pin for return. A minimum voltage of 4.6V
at VCCDR pin is required to start operations of the device.
The controller embodies a sophisticated anti-shoot-through system to minimize low side body diode con-
duction time maintaining good efficiency saving the use of Schottky diodes. The dead time is reduced to
few nanoseconds assuring that high-side and low-side mosfets are never switched on simultaneously:
when the high-side mosfet turns off, the voltage on its source begins to fall; when the voltage reaches 2V,
the low-side mosfet gate drive is applied with 30ns delay. When the low-side mosfet turns off, the voltage
at LGATEx pin is sensed. When it drops below 1V, the high-side mosfet gate drive is applied with a delay
of 30ns. If the current flowing in the inductor is negative, the source of high-side mosfet will never drop.
To allow the turning on of the low-side mosfet even in this case, a watchdog controller is enabled: if the
source of the high-side mosfet don't drop for more than 240ns, the low side mosfet is switched on so al-
lowing the negative current of the inductor to recirculate. This mechanism allows the system to regulate
even if the current is negative.
The BOOTx and VCCDR pins are separated from IC's power supply (VCC pin) as well as signal ground
(SGND pin) and power ground (PGND pin) in order to maximize the switching noise immunity. The sepa-
rated supply for the different drivers gives high flexibility in mosfet choice, allowing the use of logic-level
mosfet. Several combination of supply can be chosen to optimize performance and efficiency of the appli-
cation. Power conversion is also flexible; 5V or 12V bus can be chosen freely.
The peak current is shown for both the upper and the lower driver of the two phases in figure 3. A 10nF
capacitive load has been used. For the upper drivers, the source current is 1.9A while the sink current is
1.5A with V
BOOT
-V
PHASE
= 12V; similarly, for the lower drivers, the source current is 2.4A while the sink
current is 2A with VCCDR = 12V.
Figure 3. Drivers peak current: High Side (left) and Low Side (right)
V
OUT_TOT_ACC
[%] =
EXT_REF_Accuracy[%]
(
)
2
+
V
REF_IN/OUT
------------------------------------
[%]
2
+
V
EXT_REF
--------------------------
100
2
+ K
OS
V
V
OUT
--------------------
100
2
CH3 = HGATE1; CH4 = HGATE2
CH3 = LGATE1; CH4 = LGATE2
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