參數(shù)資料
型號: L6712Q
廠商: 意法半導(dǎo)體
英文描述: TWO-PHASE INTERLEAVED DC/DC CONTROLLER
中文描述: 兩相交錯DC / DC控制器
文件頁數(shù): 20/27頁
文件大?。?/td> 1074K
代理商: L6712Q
L6712A L6712
20/27
Figure 13. Current Sharing Control Loop.
Where
I
READ
is the difference between one phase current and the ideal current (I
MAX
/2).
For R
SENSE
= 4m
and I
MAX
= 40A the current sharing error is equal to 2.5%, neglecting errors due to Rg
and R
SENSE
mismatches.
Average Current Mode (ACM) Control Loop (DROOP=FB)
The average current mode control loop is reported in figure 14. The current information I
DROOP
sourced by
the DROOP pin flows into R
FB
implementing the dependence of the output voltage from the read current.
The ACM control loop gain results (obtained opening the loop after the COMP pin):
Where:
is the equivalent output resistance determined by the droop function;
Z
P
(s) is the impedance resulting by the parallel of the output capacitor (and its ESR) and the applied
load Ro;
Z
F
(s) is the compensation network impedance;
Z
L
(s) is the parallel of the two inductor impedance;
A(s) is the error amplifier gain;
V
V
OSC
is the ACM PWM transfer function where
V
OSC
is the oscillator ramp amplitude
and has a typical value of 3V
RA_Gain is the Remote Amplifier Gain.
Removing the dependence from the Error Amplifier gain, so assuming this gain high enough, the control
loop gain results:
L1
L2
+
+
PWM1
1/5
1/5
I
INFO2
I
INFO1
PWM2
COMP
V
OUT
CURRENT
SHARING
DUTY CYCLE
CORRECTION
D02IN1393
G
LOOP
s
( )
PWM Z
s
------------------------------------------------------------------+
( )
R
Z
s
A s
)
Z
P
s
( )
Z
L
s
( )
+
(
)
--------------
1
A s
( )
-----------
+
R
FB
+
=
R
DROOP
Rg
----------------------
R
FB
=
PWM
4
5
--
-------------------
=
G
LOOP
s
( )
4
5
--
V
V
OSC
-------------------
Z
s
( )
Z
L
s
+
Z
P
s
( )
------------------------------------
Rg
-------
RA_Gain Z
--------------------------------------------
s
( )
R
FB
+
=
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