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參數(shù)資料
| 型號： | L6610DTR |
| 廠商： | 意法半導體 |
| 英文描述： | CAP CER 2400PF 50V 5% C0G 0805 |
| 中文描述： | 數(shù)字可編程控制器二次內(nèi)務管理 |
| 文件頁數(shù)： | 6/29頁 |
| 文件大?。?/td> | 544K |
| 代理商： | L6610DTR |
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L6610
6/29
ABSOLUTE MAXIMUM RATINGS
THERMAL DATA
(*) mounted on board
Debounce
The PS-ON signal input has debounce logic to prevent improper activation. All of the monitored
inputs have digital filtering/debounce logic on board for high noise immunity.
AC-hysteresis
AC sense hysteresis. Programmable hysteresis is provided on the ACsns input (#13) to avoid
undesired shutdown caused by noise as the voltage at the pin is near the threshold or by the
voltage ripple across the bulk capacitor.
Vdd-OVP
Vdd is monitored for overvoltage. If an overvoltage is detected, MFAULT (#1) and DFAULT (#11)
are latched high.
Vdd-UVL
To prevent false signals of any of IC’s output pins, an under voltage lock-out circuit monitors Vdd
and keeps all IC’s output at their default OFF level until Vdd reaches a sufficient minimum
voltage for ensuring integrity. When Vdd goes below the UV threshold, all latches are reset and
volatile programming memory cleared.
Dual-OVP
Dmon (#10) is monitored to detect an overvoltage condition; in this case MFAULT (#1) and
DFAULT (#11) are latched high.
Dual-UVP
Dmon (#10) is monitored to detect an undervoltage condition; in this case MFAULT (#1) is
latched high and Cout (#8) is pulled low.
Soft-start
The IC provides an on-board 8ms soft-start, a quasi-monotonic ramp from 0V to 2.5V for the A
error amplifier reference voltage, in order to avoid high current peaks in the primary circuit and
output voltage overshoots at start-up. In fact, if this reference gets the nominal value as soon as
the power-up occurs, the A E/A will go out of regulation and tend to sink much more current, thus
forcing PWM to work with the maximum duty-cycle.
Bounce or
Latch-mode
This option allows setting either latched-mode or auto restart after 1 second delay in case of
overcurrent and undervoltage faults.
Symbol
Parameter
Value
Unit
Vdd
Supply voltage
-0.5 to +7
V
Voltage on PROG, PS-ON/Clock, DFAULT, VREF, and error
amplifier pins
-0.5 to Vdd+0.5
V
Voltage on MFAULT, PW-OK, Dmon and positive UV, OV, OC, AC
sense pins.
-0.5 to +16
V
Voltage on -5V and -12V UV/OV sense pins
-16 to +5
V
Maximum current in ESD clamp diodes
10
mA
T
J
Operating Junction Temperature
-25 to 150
°C
T
STO
Storage Temperature
-50 to 150
°C
T
L
Lead Temperature (soldering, 10 seconds)
300
°C
Symbol
Parameter
SDIP24
SO24
Unit
R
th j-amb
Max. Thermal Resistance junction-to-ambient (*)
70
90
°C/W
FUNCTION DESCRIPTION
(continued)
Name
Description
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| L6611N | DIGITALLY PROGRAMMABLE SECONDARY HOUSEKEEPING CONTROLLER |
相關代理商/技術參數(shù) |
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| L6610N | 功能描述:IC CTRLR HOUSEKEEPING BCD 24-DIP RoHS:是 類別:集成電路 (IC) >> PMIC - 電源控制器，監(jiān)視器 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 應用:多相控制器 輸入電壓:- 電源電壓:9 V ~ 14 V 電流 - 電源:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:40-WFQFN 裸露焊盤 供應商設備封裝:40-TQFN-EP（5x5） 包裝:帶卷 (TR) |
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| L6611DTR | 功能描述:IC CTRLR HOUSEKEEPING 20SOIC RoHS:否 類別:集成電路 (IC) >> PMIC - 電源控制器，監(jiān)視器 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 應用:多相控制器 輸入電壓:- 電源電壓:9 V ~ 14 V 電流 - 電源:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:40-WFQFN 裸露焊盤 供應商設備封裝:40-TQFN-EP（5x5） 包裝:帶卷 (TR) |
| L6611N | 功能描述:IC CTRLR HOUSEKEEPING BCD 20-DIP RoHS:是 類別:集成電路 (IC) >> PMIC - 電源控制器，監(jiān)視器 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 應用:多相控制器 輸入電壓:- 電源電壓:9 V ~ 14 V 電流 - 電源:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:40-WFQFN 裸露焊盤 供應商設備封裝:40-TQFN-EP（5x5） 包裝:帶卷 (TR) |
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