參數(shù)資料
型號(hào)： L652DU90RF
廠商： Advanced Micro Devices, Inc.
英文描述： 128 Megabit (16 M x 8-Bit) CMOS 3.0 Volt-only Uniform Sector Flash Memory with VersatileIO⑩ Control
中文描述： 128兆位（16米× 8位）的CMOS 3.0伏特，只有統(tǒng)一部門閃存與VersatileIO⑩控制記憶
文件頁(yè)數(shù)： 34/54頁(yè)
文件大小： 492K
代理商： L652DU90RF
32
Am29LV652D
24961A5 May 5, 2006
D A T A S H E E T
RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output which
indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY# status is valid after
the rising edge of the final WE# pulse in the command
sequence. Since RY/BY# is an open-drain output, sev-
eral RY/BY#s can be tied together in parallel with a
pull-up resistor to V
CC
.
If the output is low (Busy), the device is actively eras-
ing or programming. (This includes programming in
the Erase Suspend mode.) If the output is high
(Ready), the device is in the read mode, the standby
mode, or the device is in the erase-suspend-read
mode.
Table 11, on page 34
shows the outputs for RY/BY#.
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or com-
plete, or whether the device has entered the Erase
Suspend mode. Toggle Bit I may be read at any ad-
dress, and is valid after the rising edge of the final
WE# pulse in the command sequence (prior to the
program or erase operation), and during the sector
erase time-out.
During an Embedded Program or Erase algorithm op-
eration, successive read cycles to any address cause
DQ6 to toggle. The system may use either OE# or
CE# (or CE2#) to control the read cycles. When the
operation is complete, DQ6 stops toggling.
After an erase command sequence is written, if all sectors
selected for erasing are protected, DQ6 toggles for approxi-
mately 100 μs, then returns to reading array data. If not all
selected sectors are protected, the Embedded Erase algo-
rithm erases the unprotected sectors, and ignores the se-
lected sectors that are protected.
The system can use DQ6 and DQ2 together to determine
whether a sector is actively erasing or is erase-suspended.
When the device is actively erasing (that is, the Embedded
Erase algorithm is in progress), DQ6 toggles. When the de-
vice enters the Erase Suspend mode, DQ6 stops toggling.
However, the system must also use DQ2 to determine
which sectors are erasing or erase-suspended. Alterna-
tively, the system can use DQ7 (see the subsection on
“DQ7: Data# Polling” on page 31
).
If a program address falls within a protected sector,
DQ6 toggles for approximately 1
μ
s after the program
command sequence is written, then returns to reading
array data.
DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded Pro-
gram algorithm is complete.
Table 11, on page 34
shows the outputs for Toggle Bit
I on DQ6.
Figure 6
shows the toggle bit algorithm.
Fig-
ure 19, on page 45
in the “AC Characteristics” section
shows the toggle bit timing diagrams.
Figure 20, on
page 45
shows the differences between DQ2 and DQ6
in graphical form. See also the subsection
“DQ2: Tog-
gle Bit II” on page 33
.
Figure 6.
Toggle Bit Algorithm
START
No
Yes
Yes
DQ5 = 1
No
Yes
Toggle Bit
= Toggle
No
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Read DQ7–DQ0
Toggle Bit
= Toggle
Read DQ7–DQ0
Twice
Read DQ7–DQ0
Note:
The system should recheck the toggle bit even if
DQ5 = “1” because the toggle bit may stop toggling as DQ5
changes to “1.” See the subsections on DQ6 and DQ2 for
more information.
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