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參數(shù)資料
| 型號(hào)： | L64250JC20 |
| 廠商： | Innovasic Semiconductor |
| 英文描述： | Histogram/Hough Transform Processor |
| 中文描述： | 直方圖/ Hough變換處理器 |
| 文件頁數(shù)： | 5/21頁 |
| 文件大小： | 100K |
| 代理商： | L64250JC20 |
IA64250
Histogram/Hough Transform Processor
I/O SIGNAL DESCRIPTION:
The diagram below describes the I/O characteristics for each signal on the IC. The signal
names correspond to the signal names on the pinout diagrams provide.
I/O Characteristics:
Data Sheet
As of Production Ver. 01
Copyright
2000
innov
ASIC
The End of Obsolescence
ENG211001219-01
www.innovasic.com
Customer Support:
Page 5 of 21
1-888-824-4184
IODV
VDO.0 - VDO.8
CIO.0 - CIO.8
WE
REGADR.0- REGADR.5
O
O
I
I
I
When HIGH, ACC RAM or LUT RAM dataon theDO busisvaid.
LUT RAM dataoutput (usesCLK1).
Control register and LUT input databus.
Used to strobedatainto modelatches when LOW.
Seects modelatch, marker or maximumregisters.
Seects marker and maximumregisters when HIGH or modelatches when LOW.
AT must beLOW to accesstheLUT or ACC RAMsviatheDO bus.
Pixe clock activeat rising edge
User I/O clock (may beconnected to CLK1)
AT
I
CLK1
I
CLK2
STARTIO
CX,CY
RX,RY
RESET FP
I
I
I
I
I
Initiates RAM I/O at HIGH to LOW transition.
Used to increment X or Y counters when HIGH.
Resets X or Y counters(overrides CX, CY) when HIGH.
ResetsFP counter when HIGH.
Test pin shoud beleft unconnected.
PO
O
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