![](http://datasheet.mmic.net.cn/330000/L64105_datasheet_16421502/L64105_445.png)
Index
IX-29
internal clock synchronization
4-44
PCM FIFO buffer
4-77
play mode
4-78
RAM test
4-93
repeat frame
4-51
rip forward mode
4-52
,
4-53
skip frame
4-50
soft mute
4-78
user data FIFO
4-18
,
8-22
video packet error
4-37
status bits
5-9
stereo
intensity
4-75
Ms
4-75
stereo mode
4-82
stereo subbands
4-74
stereophonic digital programs
10-29
still images
8-46
,
9-6
,
9-13
to
9-15
STM
B-8
storage
1-5
channel data
4-35
frames
1-5
frames location
8-30
frames size
8-30
OSD areas
9-24
formats
9-28
to
9-29
SDRAM addresses
9-26
pack headers
4-37
PES headers
4-36
,
6-15
unencoded serial input
2-9
video frames
7-1
storage devices
2-9
store header parameters
8-19
streams
A/V sync errors
7-7
asynchronous transfers
6-4
audio detection
4-34
audio ES channel buffer
6-20
audio ID
6-10
audio select enable
4-34
,
6-10
audio transfers
2-5
changing IDs
6-8
channel interface and
1-3
,
6-1
,
6-2
data audio encoded
A-9
data video encoded
A-9
input formats
4-12
linear PCM samples
10-15
multichannel audio
10-10
pel components
9-10
preparser transport errors
6-26
,
6-27
preparsing
6-9
,
6-18
,
6-24
to
6-25
elementary
6-12
to
6-14
MPEG-1 sequences
6-16
to
6-18
select bits
4-12
system syntax
6-2
video detection
4-35
video select enable
4-35
,
6-9
video transfers
2-5
,
2-6
subband samples
10-10
,
10-12
subband synthesis
10-12
subbands (intensity stereo)
4-74
subframes
10-31
IEC958 stream
10-30
subpixel offset
4-65
subpixel values
9-20
,
9-22
SWEn signal
2-8
description
2-8
sync active low bit
4-67
usage overview
9-10
sync word detection
10-5
synchronization, losing
10-5
synchronized presentation units
4-3
synchronizing audio and video
A-11
synchronous DRAM See SDRAM
synchronous input multiplexer
6-8
synchronous mode
6-3
,
6-5
synchronous transfers
2-6
,
4-28
,
4-29
,
4-89
,
6-5
A/V data valid
2-6
A/V event interrupts
4-6
,
4-7
A/V read compare
4-21
AC timing
11-14
audio code detect
4-4
audio sync errors
4-8
,
10-5
channel buffering
7-7
channel constraints
6-6
hardware sync controls and
2-10
input timing
9-10
,
9-11
out-of-sync conditions
10-5
PCM data
10-16
recovery bit
4-3
timing
11-15
synchronous valid signal timing diagram
6-6
SYSCLK signal
2-12
description
2-12
system channel buffer
6-16
SDRAM addresses
6-18
system channel buffer map
6-17
program streams
6-19
system clock
2-12
See also clock; device clock
System Clock Reference (SCR)
5-6
to
5-8
block diagram
5-7
compare audio interrupt
4-4
compare interrupt
4-5
compare/capture mode
4-14
compare/capture mode bits
4-13
,
5-6