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參數(shù)資料
| 型號： | L640MU90NI |
| 廠商： | Advanced Micro Devices, Inc. |
| 元件分類： | DRAM |
| 英文描述： | 64 Megabit (4 M x 16-Bit) MirrorBita?? 3.0 Volt-only Uniform Sector Flash Memory with VersatileI/Oa?? Control |
| 中文描述： | 64Mb(4個M x 16位)的MirrorBit，3V，統(tǒng)一扇區(qū)閃存并有Versatile輸入/輸出控制 |
| 文件頁數(shù)： | 12/59頁 |
| 文件大?。?/td> | 699K |
| 代理商： | L640MU90NI |
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10
Am29LV640MU
25301C5 February1,2007
D A T A S H E E T
DEVICE BUS OPERATIONS
This section describes the requirements and use of
the device bus operations, which are initiated through
the internal command register. The command register
itself does not occupy any addressable memory loca-
tion. The register is a latch used to store the com-
mands, along with the address and data information
needed to execute the command. The contents of the
register serve as inputs to the internal state machine.
The state machine outputs dictate the function of the
device.
Table 1
lists the device bus operations, the in-
puts and control levels they require, and the resulting
output. The following subsections describe each of
these operations in further detail.
Table 1.
Device Bus Operations
Legend:
L = Logic Low = V
IL
, H = Logic High = V
IH
, V
ID
= 11.5–12.5
V, V
HH
= 11.5–12.5
V, X = Don’t Care, SA = Sector Address,
A
IN
= Address In, D
IN
= Data In, D
OUT
= Data Out
Notes:
1. Addresses are A21:A0. Sector addresses are A21:A15.
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector Group
Protection and Unprotection” section.
3. D
IN
or D
OUT
as required by command sequence, data polling, or sector protect algorithm (see Figure 2).
VersatileIO
(V
IO
) Control
The VersatileIO (V
IO
) control allows the host system
to set the voltage levels that the device generates and
tolerates on CE# and DQ I/Os to the same voltage
level that is asserted on V
IO
. See
“Ordering Informa-
tion” on page 9
for V
IO
options on this device.
For example, a V
I/O
of 1.65–3.6 volts allows for I/O at
the 1.8 or 3 volt levels, driving and receiving signals to
and from other 1.8 or 3 V devices on the same data
bus.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to V
IL
. CE# is the power
control and selects the device. OE# is the output con-
trol and gates array data to the output pins. WE#
should remain at V
IH
.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
content occurs during the power transition. No com-
mand is necessary in this mode to obtain array data.
Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid
data on the device data outputs. The device remains
enabled for read access until the command register
contents are altered.
See “Reading Array Data” for more information. Refer
to the AC
Read-Only Operations
table for timing speci-
fications and to Figure 13 for the timing diagram. Refer
Operation
CE#
OE#
WE#
RESET#
ACC
Addresses
(Note 2)
DQ0–
DQ15
Read
L
L
H
H
X
A
IN
D
OUT
Write (Program/Erase)
L
H
L
H
X
A
IN
(Note 3)
Accelerated Program
L
H
L
H
V
HH
A
IN
(Note 3)
Standby
V
CC
±
0.3 V
X
X
V
CC
±
0.3 V
H
X
High-Z
Output Disable
L
H
H
H
X
X
High-Z
Reset
X
X
X
L
X
X
High-Z
Sector Group Protect (Note 2)
L
H
L
V
ID
X
SA, A6=L, A3=L,
A2=L, A1=H, A0=L
(Note 3)
Sector Group Unprotect
(Note 2)
L
H
L
V
ID
X
SA, A6=H, A3=L,
A2=L, A1=H, A0=L
(Note 3)
Temporary Sector Group
Unprotect
X
X
X
V
ID
X
A
IN
(Note 3)
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