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參數(shù)資料
| 型號(hào)： | L5996 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 5 BIT DYNAMIC DAC CONTROLLER FOR MOBILE CPU |
| 中文描述： | 5位動(dòng)態(tài)援控制器的移動(dòng)CPU |
| 文件頁數(shù)： | 6/9頁 |
| 文件大小： | 77K |
| 代理商： | L5996 |
long as the current limit value is reduced with re-
spect to the normal operating value. This is done
to limit voltage overshoots during core voltage
changes. Making this signal externally available
simplifies system debugging.
VID0-4(pin20-24):
Voltage Identification code in-
put. These open collector compatible inputs are
used to program the output voltage as specified
in Table 1. Every pin has an internal pull up. If all
four pins are high or floating, the output voltage
and the 2.5V regulator are suspended and the
POWERGOOD is low.
NOSKIP(pin25):
Pulse skipping mode control. A
high level (>2.4V) disables pulse skipping in low
load condition,a low level (>0.8V) enables it.
HSRC(pin26):
source connection. This pin provides the return
path forthe high side driver.
High
side
N-Channel
switch
HGATE(pin27)
: Gate driver output, high side N-
Channel switch. The driver internal impedance is
about 4
at VIN=12V.
HSTRAP(pin28):
Bootstrap capacitorpin. This pin
provide to supply the high side driver sinking the
current by the bootstrapcapacitor.
RSTRAP(pin29):
driver supply voltage. This pin could be con-
nected to REG5 to reduce the switching losses
due to the external Mosfets gate capacitance.
This is useful to maintain an high efficiency at
light load.
Synchronous
rectifier
gate
RGATE(pin30):
Gate driver output, low side N-
Channel switch. The driver internal impedance is
about 3
at VIN=12V.
PWRGND(pin31):
Power ground. This pin has to
be connected closely
source in order to reduce the noise injected into
the IC.
to the low side mosfet
POWER GOOD(pin32):
Open drain power good
output. This pin is pulled low if the output voltage
is not within
±
10% and the 2.5V output is lower
than 2.175V (-13%). The pin is pulled low also if
REG5, VPROG and VBG have not reached the
expected values. This test could be useful in an
assemblingfault condition.
Table 1. VID [4:0] AND corresponding +VCC_CPU_CORE ranges
VID[4:0]
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
+VCC_CPU_CORE
2.00V
1.95V
1.90V
1.85V
1.80V
1.75V
1.70V
1.65V
1.60V
1.55V
1.50V
1.45V
1.40V
1.35V
1.30V
No CPU
VID[4:0]
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
+VCC_CPU_CORE
1.275V
1.250V
1.225V
1.200V
1.175V
1.150V
1.125V
1.100V
1.075V
1.050V
1.025V
1.000V
0.975V
0.950V
0.925V
No CPU
L5996
6/9
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