參數(shù)資料
型號: L5993
廠商: 意法半導體
英文描述: CONSTANT POWER CONTROLLER
中文描述: 恒功率控制器
文件頁數(shù): 12/22頁
文件大小: 200K
代理商: L5993
Pin 12
. SGND(Signal Ground).This groundrefer-
ences the control circuitry of the IC, so all the
ground connections of the external parts related
to control functionsmust lead to this pin. In laying
out the PCB, care must be taken in preventing
switched high currents from flowing through the
SGND path.
Pin 13.
ISEN (Current Sense). This pin is to be
connected to the ”hot” lead of the current sense
resistor R
sense
(being the other one grounded),to
get a voltage ramp which is an image of the cur-
rent of the switch (I
Q
). When this voltage is equal
to:
V
13pk
=
I
Qpk
R
sense
=
V
COMP
1.4
3
(
8
)
the conductionof theswitch is terminated.
To increase the noise immunity, a ”Leading Edge
Blanking” of about 100ns is internally realized as
shown in fig. 27. Because of that, the smoothing
RC filter between this pin and R
sense
could be re-
movedor, at least,considerablyreduced.
Pin 14.
DIS (Device Disable). When the voltage
on pin 14 rises above 2.5V the IC is shut down
and it is necessaryto pull VCC (IC supply voltage,
pin 8) below the UVLO threshold to allow the de-
vice to restart.
The pin can be driven by an external logic signal
in case of power management, as shown in fig.
28. It is also possible to realize an overvoltage
protection, as shown in the section ” Application
Ideas”.Ifused, bypass this pin to ground witha fil-
ter capacitor to avoid spurious activation due to
noise spikes. If not, it must be connected to
SGND.
Pin 15.
DC-LIM (Maximum Duty Cycle Limit). The
upper extreme, Dx, of the duty cycle range de-
pends on the voltage applied to this pin. Approxi-
mately,
D
x
R
T
R
T
+
230
(
9
)
if DC-LIM is grounded or left floating. Instead,
connecting DC-LIM to VREF (half duty cycle op-
tion),Dx will be setapproximately to:
D
x
R
T
2
R
T
+
260
(
10
)
and the output switching frequency will be halved
with respect to the oscillator one because an in-
ternal T flip-flop (see block diagram, fig. 1) is acti-
vated.Fig. 29 showsthe operation.
The half duty cycle option speeds up the dis-
charge of the timing capacitor C
T
(in order to get
duty cycles as close as possible to 50%) so the
oscillator frequency - with the same R
T
and C
T
-
will be slightly higher.
The halving of frequency can be used to reduce
losses at light load in all those systems that must
comply with requirements regarding energy con-
sumption (e.g. monitor displays, see ”Application
Ideas”).
+
-
I
D97IN503
ISEN
0
3V
CLK
2V
+
-
+
-
1.2V
FROM E/A
OVERCURRENT
COMPARATOR
PWM
COMPARATOR
TO
PWM
LOGIC
TO FAULT
LOGIC
13
Figure 27. Internal LEB.
+
-
C
D97IN502
DIS
D
R
Q
DISABLE
UVLO
2.5V
14
DISABLE
SIGNAL
Figure28. Disable (Latched)
L5993
12/22
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