參數(shù)資料
型號(hào)： L4977A
廠商： 意法半導(dǎo)體
英文描述： Power Switching Regulator(功率開(kāi)關(guān)穩(wěn)壓器)
中文描述： 電源開(kāi)關(guān)穩(wěn)壓器（功率開(kāi)關(guān)穩(wěn)壓器）
文件頁(yè)數(shù)： 3/21頁(yè)
文件大?。?/td> 287K
代理商： L4977A
CIRCUIT OPERATION
(refer to the block dia-
gram)
The L4977Ais a 7A monolithic stepdownswitching
regulator working in continuous mode realized in
the new BCD Technology. This technology allows
the integration of isolated vertical DMOS power
transistorsplus mixed CMOS/Bipolartransistors.
The device can deliver 7A at an output voltage
adjustable from 5.1V to 40V, and contains diag-
nostic and control functions that make it particu-
larlysuitable for microprocessor basedsystems.
BLOCK DIAGRAM
The block diagram shows the DMOS power tran-
sistor and the PWM control loop. Integrated func-
tions include a referencevoltage trimmed to 5.1V
±
2%, soft start, undervoltage lockout, oscillator
with feedforward control, pulse by pulse current
limit, thermal shutdown and finally the reset and
power fail circuit. The reset and power fail circuit
provides an output signal for a microprocessor in-
dicatingthe statusof the system.
Device turn on is around 11V with a typical 1V
hysteresis, this threshold provides a correct volt-
age for the driving stage of the DMOS gate and
the hysteresispreventsinstabilities.
An external bootstrap capacitor charged to 12V
by an internal voltage reference is needed to pro-
vide correct gate drive to the power DMOS. The
driving circuit is able to source and sink peak cur-
rents of around 0.5A to the gate of the DMOS
transistor. A typical switching time of the current
in the DMOS transistor is 50ns. Due to the fast
commutation switching frequencies up to 500kHz
arepossible.
The PWM control loop consists of a sawtooth os-
cillator, error amplifier, comparator, latch and the
output stage. An error signal is producedby com-
paring the output voltage with the precise 5.1V
±
2% on chip reference. This error signal is then
compared with the sawtooth oscillator, in order to
generatea fixed frequencypulse width modulated
drive for the output stage. A PWM latch is in-
cluded to eliminate multiple pulsing within a pe-
riod even in noisy environments. The gain and
PIN FUNCTIONS
N
o
Name
Function
1
OSCILLATOR
R
osc
. External resistor connected to ground determines the constantcharging
current of C
osc
.
2
OSCILLATOR
C
osc
. External capacitor connected to grounddetermines (with R
osc
) the
switching frequency.
3
RESET INPUT
Input of Power Fail Circuit. The threshold is 5.1V. It may be connected via a
dividerto the input for power failfunction. It must be connected to the pin 14 an
external 30K
resistorwhen power fail signal not required.
4
RESET OUT
Open Collector Reset/power Fail Signal Output. This output ishigh when the
supply and the output voltages are safe.
5
RESET DELAY
A C
d
capacitor connected between this terminal and ground determines the
reset signaldelay time.
6
BOOTSTRAP
A C
boot
capacitor connected between this terminal and the output allows to
drive properly the internal D-MOS transistor.
7
OUTPUT
Regulator Output.
8
GROUND
Common Ground Terminal
9
SUPPLY VOLTAGE
Unregulated Input Voltage.
10
FREQUENCY
COMPENSATION
A series RC network connected between this terminal and ground determines
the regulation loop gain characteristics.
11
FEEDBACK INPUT
The Feedback Terminal of the Regulation Loop. The output is connected
directly to this terminal for 5.1V operation; It is connected via adivider for higher
voltages.
12
SOFT START
Soft Start Time Constant.A capacitor is connected between thi sterminal and
ground to define the soft start time constant.
13
SYNC INPUT
MultipleL4977A are synchronized by connecting pin 13inputs together or via
an external syncr. pulse.
14
V
ref
5.1V V
ref
Device Reference Voltage.
15
V
start
Internal Start-up Circuit to Drive the Power Stage.
L4977A
3/21
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