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| 型號： | L320ML12NI |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | 32 Megabit (2 M x 16-Bit/4 M x 8-Bit) MirrorBit⑩ 3.0 Volt-only Uniform Sector Flash Memory with VersatileI/O⑩ Control |
| 中文描述： | 32兆位（2米× 16位/ 4米× 8位）的MirrorBit⑩3.0伏特，只有統(tǒng)一閃存部門與VersatileI /輸出⑩控制 |
| 文件頁數(shù)： | 27/59頁 |
| 文件大小： | 657K |
| 代理商： | L320ML12NI |
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January31,2007 26517B4
Am29LV320MH/L
25
D A T A S H E E T
Enter Secured Silicon Sector/Exit Secured
Silicon Sector Command Sequence
The Secured Silicon Sector region provides a secured
data area containing an 8-word/16-byte random Elec-
tronic Serial Number (ESN). The system can access
the Secured Silicon Sector region by issuing the
three-cycle Enter Secured Silicon Sector command
sequence. The device continues to access the Se-
cured Silicon Sector region until the system issues the
four-cycle Exit Secured Silicon Sector command se-
quence. The Exit Secured Silicon Sector command
sequence returns the device to normal operation. Ta-
bles
10
and
11
show the address and data require-
ments for both command sequences. See also
“Secured Silicon Sector Flash Memory Region”
for fur-
ther information.
Note that the ACC function and un-
lock bypass modes are not available when the
Secured Silicon Sector is enabled.
Word/Byte Program Command Sequence
Programming is a four-bus-cycle operation. The pro-
gram command sequence is initiated by writing two
unlock write cycles, followed by the program set-up
command. The program address and data are written
next, which in turn initiate the Embedded Program al-
gorithm. The system is
not
required to provide further
controls or timings. The device automatically provides
internally generated program pulses and verifies the
programmed cell margin. Tables
10
and
11
show the
address and data requirements for the word/byte pro-
gram command sequence, respectively.
Note that the
Secured Silicon Sector, autoselect, and CFI functions
are unavailable when a program operation is in
progress.
When the Embedded Program algorithm is complete,
the device then returns to the read mode and ad-
dresses are no longer latched. The system can deter-
mine the status of the program operation by using
DQ7 or DQ6. Refer to the
Write Operation Status
sec-
tion for information on these status bits.
Any commands written to the device during the Em-
bedded Program Algorithm are ignored.
Note that a
hardware reset
immediately terminates the program
operation. The program command sequence should
be reinitiated once the device has returned to the read
mode, to ensure data integrity.
Programming is allowed in any sequence and across
sector boundaries.
A bit cannot be programmed
from “0” back to a “1.”
Attempting to do so may
cause the device to set DQ5 = 1, or cause the DQ7
and DQ6 status bits to indicate the operation was suc-
cessful. However, a succeeding read will show that the
data is still “0.” Only erase operations can convert a “0”
to a “1.”
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to pro-
gram words to the device faster than using the stan-
dard program command sequence. The unlock bypass
command sequence is initiated by first writing two un-
lock cycles. This is followed by a third write cycle con-
taining the unlock bypass command, 20h. The device
then enters the unlock bypass mode. A two-cycle un-
lock bypass program command sequence is all that is
required to program in this mode. The first cycle in this
sequence contains the unlock bypass program com-
mand, A0h; the second cycle contains the program
address and data. Additional data is programmed in
the same manner. This mode dispenses with the initial
two unlock cycles required in the standard program
command sequence, resulting in faster total program-
ming time. Tables
10
and
11
show the requirements
for the command sequence.
During the unlock bypass mode, only the Unlock By-
pass Program and Unlock Bypass Reset commands
are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset com-
mand sequence. The first cycle must contain the data
90h. The second cycle must contain the data 00h. The
device then returns to the read mode.
Write Buffer Programming
Write Buffer Programming allows the system write to a
maximum of 16 words/32 bytes in one programming
operation. This results in faster effective programming
time than the standard programming algorithms. The
Write Buffer Programming command sequence is initi-
ated by first writing two unlock cycles. This is followed
by a third write cycle containing the Write Buffer Load
command written at the Sector Address in which pro-
gramming will occur. The fourth cycle writes the sector
address and the number of word locations, minus one,
to be programmed. For example, if the system will pro-
gram 6 unique address locations, then 05h should be
written to the device. This tells the device how many
write buffer addresses will be loaded with data and
therefore when to expect the Program Buffer to Flash
command. The number of locations to program cannot
exceed the size of the write buffer or the operation will
abort.
The fifth cycle writes the first address location and
data to be programmed. The write-buffer-page is se-
lected by address bits A
MAX
–A
4
. All subsequent ad-
dress/data
pairs
must
selected-write-buffer-page. The system then writes the
remaining address/data pairs into the write buffer.
Write buffer locations may be loaded in any order.
fall
within
the
The write-buffer-page address must be the same for
all address/data pairs loaded into the write buffer.
(This means Write Buffer Programming cannot be per-
formed across multiple write-buffer pages. This also
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| L320ML12PF | 32 Megabit (2 M x 16-Bit/4 M x 8-Bit) MirrorBit⑩ 3.0 Volt-only Uniform Sector Flash Memory with VersatileI/O⑩ Control |
| L320ML12PI | 32 Megabit (2 M x 16-Bit/4 M x 8-Bit) MirrorBit⑩ 3.0 Volt-only Uniform Sector Flash Memory with VersatileI/O⑩ Control |
| L320ML90NF | 32 Megabit (2 M x 16-Bit/4 M x 8-Bit) MirrorBit⑩ 3.0 Volt-only Uniform Sector Flash Memory with VersatileI/O⑩ Control |
| L320ML90NI | 32 Megabit (2 M x 16-Bit/4 M x 8-Bit) MirrorBit⑩ 3.0 Volt-only Uniform Sector Flash Memory with VersatileI/O⑩ Control |
| L4401DW1T1 | Silicon PNP Epitaxial Planer Transistor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| L320ML12PF | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:32 Megabit (2 M x 16-Bit/4 M x 8-Bit) MirrorBit⑩ 3.0 Volt-only Uniform Sector Flash Memory with VersatileI/O⑩ Control |
| L320ML12PI | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:32 Megabit (2 M x 16-Bit/4 M x 8-Bit) MirrorBit⑩ 3.0 Volt-only Uniform Sector Flash Memory with VersatileI/O⑩ Control |
| L320ML90NF | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:32 Megabit (2 M x 16-Bit/4 M x 8-Bit) MirrorBit⑩ 3.0 Volt-only Uniform Sector Flash Memory with VersatileI/O⑩ Control |
| L320ML90NI | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:32 Megabit (2 M x 16-Bit/4 M x 8-Bit) MirrorBit⑩ 3.0 Volt-only Uniform Sector Flash Memory with VersatileI/O⑩ Control |
| L-320X | 制造商:COOPER INDUSTRIES 功能描述:BIT 1/4 HEX DRV POWER # .036 |
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