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參數(shù)資料
| 型號： | L10C11JC20 |
| 廠商： | LOGIC DEVICES INC |
| 元件分類： | 數(shù)字信號處理外設(shè) |
| 英文描述： | 4/8-bit Variable Length Shift Register |
| 中文描述： | 8-BIT, DSP-PIPELINE REGISTER, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數(shù)： | 4/6頁 |
| 文件大?。?/td> | 66K |
| 代理商： | L10C11JC20 |
DEVICES INCORPORATED
L10C11
4/8-bit Variable Length Shift Register
Pipeline Registers
03/27/2000–LDS.11-L
4
1. Maximum Ratings indicate stress
specifications only. Functional oper-
ation of these products at values be-
yond those indicated in the Operating
Conditions table is not implied. Expo-
sure to maximum rating conditions for
extended periods may affect reliability.
2. The products described by this speci-
fication include internal circuitry de-
signed to protect the chip from damaging
substrate injection currents and accumu-
lations of static charge. Nevertheless,
conventional precautions should be ob-
served during storage, handling, and use
of these circuits in order to avoid expo-
sure to excessive electrical stress values.
3. This device provides hard clamping of
transient undershoot and overshoot. In-
put levels below ground or above
V
CC
will be clamped beginning at –0.6V and
V
CC
+ 0.6 V. The device can withstand
indefinite operation with inputs in the
range of –0.5 V to +7.0 V. Device opera-
tion will not be adversely affected, how-
ever, input current levels will be well in
excess of 100 mA.
4. Actual test conditions may vary from
those designated but operation is guar-
anteed as specified.
5. Supply current for a given application
can be accurately approximated by:
where
N = total number of device outputs
C = capacitive load per output
V = supply voltage
F = clock frequency
6. Tested with all outputs changing ev-
ery cycle and no load, at a 5 MHz clock
rate.
7. Tested with all inputs within 0.1 V of
V
CC
or Ground, no load.
8. These parameters are guaranteed
but not 100% tested.
NCV F
4
NOTES
9. AC specifications are tested with
input transition times less than 3 ns,
output reference levels of 1.5 V (except
t
DIS
test), and input levels of nominally
0to 3.0 V. Output loading may be a
resistive divider which provides for
specified
I
OH
and
I
OL
at an output
voltage of
V
OH
min and
V
OL
max
respectively. Alternatively, a diode
bridge with upper and lower current
sources of
I
OH
and
I
OL
respectively,
and a balancing voltage of 1.5 V may be
used. Parasitic capacitance is 30 pF
minimum, and may be distributed.
This device has high-speed outputs ca-
pable of large instantaneous current
pulses and fast turn-on/ turn-off times.
As a result, care must be exercised in the
testing of this device. The following
measures are recommended:
a. A 0.1 μF ceramic capacitor should be
installed between
V
CC
and Ground
leads as close to the Device Under Test
(DUT) as possible. Similar capacitors
should be installed between device
V
CC
and the tester common, and device
ground and tester common.
b. Ground and
V
CC
supply planes
must be brought directly to the DUT
socket or contactor fingers.
c. Input voltages should be adjusted to
compensate for inductive ground and
V
CC
noise to maintain required DUT input
levels relative to the DUT ground pin.
10. Each parameter is shown as a min-
imum or maximum value. Input re-
quirements are specified from the point
of view of the external system driving
the chip. Setup time, for example, is
specified as a minimum since the exter-
nal system must supply at least that
much time to meet the worst-case re-
quirements of all parts. Responses from
the internal circuitry are specified from
the point of view of the device. Output
delay, for example, is specified as a
maximum since worst-case operation of
any device always provides data within
that time.
11. For the
t
ENA
test, the transition is
measured to the 1.5 V crossing point
with datasheet loads. For the
t
DIS
test,
the transition is measured to the
±200mV level from the measured
steady-state output voltage with
±10mA loads. The balancing volt-
age, V
TH
, is set at 3.5 V for Z-to-0
and 0-to-Z tests, and set at 0 V for Z-
to-1 and 1-to-Z tests.
12. These parameters are only tested at
the high temperature extreme, which is
the worst case for leakage current.
S1
I
OH
I
OL
V
TH
C
L
DUT
OE
0.2 V
t
DIS
t
ENA
0.2 V
1.5 V
1.5 V
3.5V Vth
1
Z
0
Z
Z
1
Z
0
1.5 V
1.5 V
0V Vth
V
OL
*
V
OH
*
V
OL
*
V
OH
*
Measured V
OL
with I
OH
= –10mA and I
OL
= 10mA
Measured V
OH
with I
OH
= –10mA and I
OL
= 10mA
F
IGURE
B. T
HRESHOLD
L
EVELS
F
IGURE
A. O
UTPUT
L
OADING
C
IRCUIT
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