hbwhelp@micrel.com or (408) 955-1690 For 100BASE-FX o" />
參數(shù)資料
型號: KSZ8993F
廠商: Micrel Inc
文件頁數(shù): 20/100頁
文件大?。?/td> 0K
描述: IC CONV MED 10/100 3PORT 128PQFP
標(biāo)準(zhǔn)包裝: 66
系列: *
類型: *
應(yīng)用: *
安裝類型: 表面貼裝
封裝/外殼: 128-BFQFP
供應(yīng)商設(shè)備封裝: 128-PQFP(14x20)
包裝: 散裝
產(chǎn)品目錄頁面: 1081 (CN2011-ZH PDF)
其它名稱: 576-1033
Micrel, Inc.
KS8993F/FL
June 2009
26
M9999-062509
hbwhelp@micrel.com or (408) 955-1690
For 100BASE-FX operation, the KS8993F FXSD1 (fiber signal detect) input pin is usually connected to the fiber
transceiver SD (signal detect) output pin. 100BASE-FX mode is activated when FXSD1 is greater than 1V. When
FXSD1 is between 1V and 1.8V, no fiber signal is detected and a Far-End Fault is generated if the feature is enabled.
Alternatively, FXSD1 can be tied high to force 100BASE-FX mode if the Far-End Fault feature is not used. When
FXSD1 is greater than 2.2V, the fiber signal is detected.
100BASE-FX signal detection is summarized in the following table.
Table 1: FX and TX Mode Selection
FXSD1 (pin 44)
Condition
Less than 0.2V
TX mode
Greater than 1V, but less than 1.8V
FX mode
No signal detected;
Far-End Fault generated (if enabled)
Greater than 2.2V
FX mode
Signal detected
To ensure proper operation, a resistive voltage divider is recommended to adjust the fiber transceiver SD output
voltage swing to match the KS8993F FXSD1 input voltage threshold. Refer to KS8993F schematic for recommended
fiber transceiver connections.
2.3.6
100BASE-FX Far-End Fault (FEF)
Far-End Fault (FEF) occurs when the signal detection is logically false on the receive side of the fiber transceiver. The
KS8993F detects a FEF when its FXSD1 input is between 1.0V and 1.8V. When a FEF occurs, the transmission side
signals the link partner by sending 84 ones followed by 1 zero in the idle period between frames.
Upon receiving a FEF, the link will go down (even when the fiber signal is detected) to indicate a fault condition. The
transmitting side is not affected when a FEF is received, and will continue to send out its normal transmit pattern from
the MAC.
By default, FEF is enabled. FEF can be disabled through register setting.
2.3.7
10BASE-T Transmit and Receive
The output 10BASE-T driver is incorporated into the 100BASE-TX driver to allow transmission with the same magnetic.
They are internally wave-shaped and pre-emphasized into outputs with a typical 2.3 V amplitude.
The harmonic
contents are at least 27 dB below the fundamental when driven by an all-ones Manchester-encoded signal.
On the receive side, input buffer and level detecting squelch circuits are employed. A differential input receiver circuit
and a PLL perform the decoding function. The Manchester-encoded data stream is separated into clock signal and
NRZ data. A squelch circuit rejects signals with levels less than 400 mV or with short pulse widths in order to prevent
noises at the RXP or RXM input from falsely triggering the decoder. When the input exceeds the squelch limit, the PLL
locks onto the incoming signal and the KS8993F decodes a data frame. The receiver clock is maintained active during
idle periods in between data reception.
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