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參數資料
| 型號： | KSZ8863FLL |
| 廠商： | Micrel Inc |
| 文件頁數： | 54/106頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ETHERNET SW 3PORT 48-LQFP |
| 產品培訓模塊： | KSZ8863 Ethernet Switch |
| 特色產品： | KSZ8863MLL, KSZ8863RLL and KSZ8863FLL Series |
| 標準包裝： | 250 |
| 控制器類型： | 以太網開關控制器 |
| 接口： | MII |
| 電源電壓： | 1.8V，2.5V，3.3V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應商設備封裝： | 48-LQFP（7x7） |
| 包裝： | 托盤 |
| 產品目錄頁面： | 1081 (CN2011-ZH PDF) |
| 配用： | 576-3866-ND - BOARD EVALUATION FOR KSZ8863FLL |
| 其它名稱： | 576-3576 |
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PIC16C72 Series
DS39016A-page 50
Preliminary
1998 Microchip Technology Inc.
8.4.1.3
TRANSMISSION
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address is
loaded into the SSPBUF register. The ACK pulse will
be sent on the ninth bit, and pin RC3/SCK/SCL is held
low. The transmit data must be loaded into the SSP-
BUF register, which also loads the SSPSR register.
Then pin RC3/SCK/SCL should be enabled by setting
bit CKP (SSPCON<4>). The master must monitor the
SCL pin prior to asserting another clock pulse. The
slave devices may be holding off the master by stretch-
ing the clock. The eight data bits are shifted out on the
falling edge of the SCL input. This ensures that the SDA
signal is valid during the SCL high time (Figure 8-9).
An SSP interrupt is generated for each data transfer
byte. Flag bit SSPIF must be cleared in software, and
the SSPSTAT register is used to determine the status
of the byte. Flag bit SSPIF is set on the falling edge of
the ninth clock pulse.
As a slave-transmitter, the ACK pulse from the master-
receiver is latched on the rising edge of the ninth SCL
input pulse. If the SDA line was high (not ACK), then the
data transfer is complete. When the ACK is latched by
the slave, the slave logic is reset (resets SSPSTAT reg-
ister) and the slave then monitors for another occur-
rence of the START bit. If the SDA line was low (ACK),
the transmit data must be loaded into the SSPBUF reg-
ister, which also loads the SSPSR register. Then pin
RC3/SCK/SCL should be enabled by setting bit CKP.
FIGURE 8-9:
I2C WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)
SDA
SCL
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
CKP (SSPCON<4>)
A7
A6
A5
A4
A3
A2
A1
ACK
D7
D6
D5
D4
D3
D2
D1
D0
ACK
Transmitting Data
R/W = 1
Receiving Address
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
P
cleared in software
SSPBUF is written in software
From SSP interrupt
service routine
Set bit after writing to SSPBUF
S
Data in
sampled
SCL held low
while CPU
responds to SSPIF
(the SSPBUF must be written-to
before the CKP bit can be set)
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相關代理商/技術參數 |
參數描述 |
|---|---|
| KSZ8863FLL-EVAL | 功能描述:以太網開發(fā)工具 3-Port 10/100 Ethernet Switch with 1x FX Port and 1x TX Port - Evaluation Board RoHS:否 制造商:Micrel 產品:Evaluation Boards 類型:Ethernet Transceivers 工具用于評估:KSZ8873RLL 接口類型:RMII 工作電源電壓: |
| KSZ8863FLLI | 功能描述:以太網 IC 3-Port 10/100 Ethernet Switch w/ 1x FX Port and 1x TX Port (Industrial Grade) RoHS:否 制造商:Micrel 產品:Ethernet Switches 收發(fā)器數量:2 數據速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| KSZ8863MLL | 功能描述:以太網 IC 3-Port Copper 10/100 Ethernet Switch with 1x MII Interface (Lead Free) RoHS:否 制造商:Micrel 產品:Ethernet Switches 收發(fā)器數量:2 數據速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| KSZ8863MLL-EVAL | 功能描述:以太網開發(fā)工具 3-Port Copper 10/100 Ethernet Switch with 1x MII Interface - Evaluation Board RoHS:否 制造商:Micrel 產品:Evaluation Boards 類型:Ethernet Transceivers 工具用于評估:KSZ8873RLL 接口類型:RMII 工作電源電壓: |
| KSZ8863MLLI | 功能描述:以太網 IC 3-Port Copper 10/100 Ethernet Switch w/ 1x MII Interface (Industrial Grade) RoHS:否 制造商:Micrel 產品:Ethernet Switches 收發(fā)器數量:2 數據速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
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