參數(shù)資料
型號(hào): KSZ8842-16MBL
廠商: Micrel Inc
文件頁數(shù): 31/141頁
文件大小: 0K
描述: IC MAC CTLR 2PORT ETH 100-LFBGA
標(biāo)準(zhǔn)包裝: 260
控制器類型: 以太網(wǎng)開關(guān)控制器
接口: PCI
電源電壓: 3.1 V ~ 3.5 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 100-LBGA
供應(yīng)商設(shè)備封裝: 100-LFBGA
包裝: 托盤
產(chǎn)品目錄頁面: 1081 (CN2011-ZH PDF)
配用: 576-1635-ND - BOARD EVALUATION KSZ8842-16MVL
576-1634-ND - BOARD EVALUATION KSZ8842-16MQL
其它名稱: 576-3076
Micrel, Inc.
KSZ8842-16/32 MQL/MVL/MVLI/MBL
October 2007
126
M9999-102207-1.9
Asynchronous Timing using DATACSN (KSZ8842-32MQL/MVL device only)
t3
t7
t6
t5
t4
t1
t2
valid
DATACSN
Read Data
RDN, WRN
Write Data
ARDY
(Read Cycle)
ARDY
(Write Cycle)
t8
t9
t10
Figure 19. Asynchronous Cycle – Using DATACSN
Symbol
Parameter
Min
Typ
Max
Unit
t1
DATACSN setup to RDN, WRN active
2
ns
t2
DATACSN hold after RDN, WRN inactive (assume
ADSN tied Low)
0
ns
t3
Read data hold to ARDY rising
0.8
ns
t4
Read data to RDN hold
4
ns
t5
Write data setup to WRN inactive
4
ns
t6
Write data hold after WRN inactive
2
ns
t7
Read active to ARDY Low
8
ns
t8
Write inactive to ARDY Low
8
ns
ARDY low (wait time) in read cycle (Note1)
(It is 0ns to read bank select register and 40ns to
read QMU data register in turbo mode) (Note2)
0
40
ns
t9
ARDY low (wait time) in read cycle (Note1)
(It is 0ns to read bank select register and 80ns to
read QMU data register in normal mode)
0
80
ns
t10
ARDY low (wait time) in write cycle (Note1)
(It is 0ns to write bank select register)
(It is 85ns to write QMU data register)
0
50
ns
Note 1: When CPU finished current Read or Write operation, it can do next Read or Write operation even the
ARDY is low. During Read or Write operation if the ADRY is low, the CPU has to keep the RDN/WRN
low until the ARDY returns to high.
Note 2: In order to speed up the ARDY low time to 40 ns, user has to use the turbo software driver which is only
supported in the A6 device. Please refer to the “KSZ88xx Programmer's Guide” for detail.
Table 26. Asynchronous Cycle using DATACSN Timing Parameters
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