參數(shù)資料
型號(hào): KSZ8841-PMQLI
廠商: Micrel Inc
文件頁(yè)數(shù): 20/74頁(yè)
文件大小: 0K
描述: IC MAC CTRLR 32BIT PCI 128-PQFP
標(biāo)準(zhǔn)包裝: 66
控制器類型: 以太網(wǎng)控制器,MAC
接口: 總線
電源電壓: 3.1 V ~ 3.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 128-BFQFP
供應(yīng)商設(shè)備封裝: 128-PQFP(14x20)
包裝: 托盤
產(chǎn)品目錄頁(yè)面: 1080 (CN2011-ZH PDF)
配用: 576-1633-ND - BOARD EVALUATION KSZ8841-PMQL
其它名稱: 576-2118
KSZ8841-PMQLI-ND
Micrel, Inc.
KSZ8841-PMQL
October 2007
27
M9999-100407-1.5
Bit
Description
29
LS Last Segment
When set, indicates that the buffer contains the last segment of a frame.
28
IPCKG IP Checksum Generate
When set, the KSZ8841-PMQL will generate correct IP checksum for outgoing frames that
contains IP protocol header. The KSZ8841-PMQL supports only a standard IP header, i.e.,
IP with a 20 byte header. When this feature is used, ADD CRC bit in the transmit mode
register should always be set.
This bit is used as a per-packet control when the IP checksum generate bit in the transmit
mode register is not set.
This bit should be always set for multiple-segment packets.
27
TCPCKG TCP Checksum Generate
When set, the KSZ8841-PMQL will generate correct TCP checksum for outgoing frames that
contains IP and TCP protocol header. The KSZ8841-PMQL supports only a standard IP
header, i.e., IP with a 20 byte header. When this feature is used, ADD CRC bit in the
transmit mode register should always be set.
This bit is used as a per-packet control when the TCP checksum generate bit in the transmit
mode register is not set.
This bit should be always set for multiple-segment packets.
26
UDPCKG UDP Checksum Generate
When set, the KSZ8841-PMQL will generate correct UDP checksum for outgoing frames that
contains an IP and UDP protocol header. The KSZ8841-PMQL supports only a standard IP
header, i.e., IP with a 20 byte header. When this feature is used, ADD CRC bit in the
transmit mode register should always be set.
This bit is used as a per-packet control when the UDP checksum generate bit in the transmit
mode register is not set.
25
TER Transmit End of Ring
When set, indicates that the descriptor pointer has reached its final descriptor.
The KSZ8841-PMQL returns to the base address of the list, forming a descriptor ring.
24
Reserved
23 – 20
SPN Switch Engine Destination Port Map
When set, this field indicates the destination port(s) where the packet will be forwarded to.
If bit 20 is set, it indicates the packet was received from port 1. If bit 21 is set, it indicates the
packet was received from port 2.
Setting all ports to 1 will cause the controller engine to broadcast the packet.
Setting all bits to 0 has no effect. The controller engine forwards the packet according to its
internal controller lookup algorithm.
This field is valid only when the last descriptor is set.
(Bits 23 and 22 are not used, but reserved for backward compatibility and future expansion.)
19 - 11
Reserved
10 - 0
TBS Transmit Buffer Size
Indicates the size, in bytes, of the transmit data buffer.
If this field is 0, the KSZ8841-PMQL ignores this buffer and moves to the next descriptor.
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