參數(shù)資料
型號: KSZ8695X-EVAL
廠商: Micrel Inc
文件頁數(shù): 38/39頁
文件大小: 0K
描述: KIT EVAL KSZ8695X EXPERIMENT
標(biāo)準(zhǔn)包裝: 1
主要目的: 接口,以太網(wǎng) PHY
嵌入式:
已用 IC / 零件: KSZ8695X
主要屬性: 單芯片網(wǎng)關(guān)解決方案
已供物品:
相關(guān)產(chǎn)品: 576-1025-ND - IC SWITCH 10/100 5PORT 208PQFP
其它名稱: 576-1624
Micrel, Inc.
KS8695X
June 2006
8
M9999-060106
Pin Number
Pin Name
Type
(1)
Pin Function
66
DATA6
I/O
External Data Bit.
67
DATA5
I/O
External Data Bit.
68
DATA4
I/O
External Data Bit.
69
DATA3
I/O
External Data Bit.
70
DATA2
I/O
External Data Bit.
71
DATA1
I/O
External Data Bit.
72
DATA0
I/O
External Data Bit.
73
VDD-IO
P
3.3V Digital I/O Circuitry VDD.
74
VSS-IO
Gnd
Digital I/O VSS.
75
ECSN2
O
External I/O Device Chip Select. Active Low.
76
ECSN1
O
External I/O Device Chip Select. Active Low.
77
ECSN0
O
External I/O Device Chip Select. Active Low.
78
EWAITN
I
External Wait. Active Low.
79
VDD-IO
P
3.3V Digital I/O Circuitry VDD.
80
VSS-IO
Gnd
Digital I/O VSS.
81
RCSN1
O
ROM/SRAM/FLASH Chip Select. Active Low.
82
RCSN0
O
ROM/SRAM/FLASH Chip Select. Active Low.
83
WRSTO
O
Watchdog Timer Reset Output.
84
TEST3
NC
This pin must be left as no connect.
85
EROEN/
WRSTPLS
O/I
ROM/SRAM/FLASH and External I/O Output Enable. Active Low. /WRSTO
Polarity Select.
86
ERWEN3/
TICTESTENN
O
External I/O and ROM/SRAM/FLASH Write Byte Enable. Active Low.
87
ERWEN2/
TESTREQA
O
External I/O and ROM/SRAM/FLASH Write Byte Enable. Active Low.
88
ERWEN1/
TESTREQB
O
External I/O and ROM/SRAM/FLASH Write Byte Enable. Active Low.
89
ERWEN0/
TESTACK
O
External I/O and ROM/SRAM/FLASH Write Byte Enable. Active Low.
90
VDD-CORE
P
1.8V Digital Core VDD.
91
VSS-CORE
Gnd
Digital Core VSS.
92
URXD
I
UART Receive Data.
93
UDTRN/
DBGENN
O
UART Data Terminal Ready. Active Low. /Debug Enable (factory test
signal).
94
UTXD
O
UART Transmit Data.
Note
:
1. Gnd = Ground.
P = Power supply.
I = Input.
O = Output.
I/O = Bidirectional.
O/I = Output in normal mode; input pin during reset.
NC = No connect.
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