參數(shù)資料
型號(hào): KSZ8051RNL
廠商: Micrel Inc
文件頁(yè)數(shù): 2/59頁(yè)
文件大?。?/td> 0K
描述: TXRX PHY 10/T100 3.3V RMII 32QFN
特色產(chǎn)品: KSZ8051RNL Physical Layer Transceiver
標(biāo)準(zhǔn)包裝: 640
類型: PHY 收發(fā)器
驅(qū)動(dòng)器/接收器數(shù): 1/1
規(guī)程: RMII
電源電壓: 1.8V,2.5V,3.3V
安裝類型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝: 32-QFN 裸露焊盤(pán)(5x5)
包裝: 托盤(pán)
其它名稱: 576-3713
Micrel, Inc.
KSZ8051MNL/RNL
July 2010
10
M9999-070910-1.0
Pin Description – KSZ8051MNL
Pin Number
Pin Name
Type
(1)
Pin Function
1
GND
Gnd
Ground
2
VDD_1.2
P
1.2V core VDD
(power supplied by KSZ8051MNL)
Decouple with 2.2uF and 0.1uF capacitors to ground.
3
VDDA_3.3
P
3.3V analog VDD
4
RXM
I/O
Physical receive or transmit signal (- differential)
5
RXP
I/O
Physical receive or transmit signal (+ differential)
6
TXM
I/O
Physical transmit or receive signal (- differential)
7
TXP
I/O
Physical transmit or receive signal (+ differential)
8
XO
O
Crystal feedback – for 25 MHz crystal
This pin is a no connect if oscillator or external clock source is used.
9
XI
I
Crystal / Oscillator / External Clock Input
25MHz +/-50ppm
10
REXT
I
Set physical transmit output current
Connect a 6.49K
Ω resistor to ground on this pin.
11
MDIO
I/O
Management Interface (MII) Data I/O
This pin has a weak pull-up, is open drain like, and requires an external 1.0K pull-
up resistor.
12
MDC
I
Management Interface (MII) Clock Input
This clock pin is synchronous to the MDIO data pin.
13
RXD3 /
PHYAD0
Ipu/O
MII Mode:
MII Receive Data Output[3]
(2) /
Config Mode:
The pull-up/pull-down value is latched as PHYADDR[0] at the
de-assertion of reset. See “Strapping Options” section for details.
14
RXD2 /
PHYAD1
Ipd/O
MII Mode:
MII Receive Data Output[2]
(2) /
Config Mode:
The pull-up/pull-down value is latched as PHYADDR[1] at the
de-assertion of reset. See “Strapping Options” section for details.
15
RXD1 /
PHYAD2
Ipd/O
MII Mode:
MII Receive Data Output[1]
(2) /
Config Mode:
The pull-up/pull-down value is latched as PHYADDR[2] at the
de-assertion of reset. See “Strapping Options” section for details.
16
RXD0 /
DUPLEX
Ipu/O
MII Mode:
MII Receive Data Output[0]
(2) /
Config Mode:
The pull-up/pull-down value is latched as DUPLEX at the
de-assertion of reset. See “Strapping Options” section for details.
17
VDDIO
P
3.3V, 2.5V or 1.8V digital VDD
18
RXDV /
CONFIG2
Ipd/O
MII Mode:
MII Receive Data Valid Output /
Config Mode:
The pull-up/pull-down value is latched as CONFIG2 at the
de-assertion of reset. See “Strapping Options” section for details.
19
RXC /
B-CAST_OFF
Ipd/O
MII Mode:
MII Receive Clock Output
Config Mode:
The pull-up/pull-down value is latched as B-CAST_OFF at the
de-assertion of reset. See “Strapping Options” section for details.
20
RXER /
ISO
Ipd/O
MII Mode:
MII Receive Error Output /
Config Mode:
The pull-up/pull-down value is latched as ISOLATE at the
de-assertion of reset. See “Strapping Options” section for details.
21
INTRP /
Ipu/Opu
Interrupt Output: Programmable Interrupt Output
This pin has a weak pull-up, is open drain like, and requires an external 1.0K pull-
up resistor.
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KSZ8051RNLI 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:10Base-T/100Base-TX Physical Layer Transceiver