參數(shù)資料
型號: KSZ8051MNL
廠商: Micrel Inc
文件頁數(shù): 57/59頁
文件大?。?/td> 0K
描述: TXRX PHY 10/T100 3.3V MII 32-QFN
標準包裝: 640
類型: PHY 收發(fā)器
驅動器/接收器數(shù): 1/1
規(guī)程: MII
電源電壓: 1.8V,2.5V,3.3V
安裝類型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤
供應商設備封裝: 32-QFN(5x5)
包裝: 托盤
配用: 576-3865-ND - BOARD EVALUATION FOR KSZ8051MNL
其它名稱: 576-3732
Micrel, Inc.
KSZ8051MNL/RNL
July 2010
7
M9999-070910-1.0
List of Figures
Figure 1. Auto-Negotiation Flow Chart................................................................................................................................. 21
Figure 2. KSZ8051MNL MII Interface .................................................................................................................................. 23
Figure 3. KSZ8051RNL RMII Interface (25MHz Clock Mode) ............................................................................................ 26
Figure 4. KSZ8051RNL RMII Interface (50MHz Clock Mode) ............................................................................................ 26
Figure 5. KSZ8051MNL/RNL and KSZ8041FTL Back-to-Back Media Converter ............................................................... 27
Figure 6. Typical Straight Cable Connection ....................................................................................................................... 29
Figure 7. Typical Crossover Cable Connection ................................................................................................................... 30
Figure 8. KSZ8051MNL/RNL Power and Ground Connections........................................................................................... 33
Figure 9. MII SQE Timing (10Base-T) ................................................................................................................................. 46
Figure 10. MII Transmit Timing (10Base-T) ......................................................................................................................... 47
Figure 11. MII Receive Timing (10Base-T) .......................................................................................................................... 48
Figure 12. MII Transmit Timing (100Base-TX)..................................................................................................................... 49
Figure 13. MII Receive Timing (100Base-TX)...................................................................................................................... 50
Figure 14. RMII Timing – Data Received from RMII............................................................................................................ 51
Figure 15. RMII Timing – Data Input to RMII ....................................................................................................................... 51
Figure 16. Auto-Negotiation Fast Link Pulse (FLP) Timing ................................................................................................. 52
Figure 17. MDC/MDIO Timing.............................................................................................................................................. 53
Figure 18. Reset Timing....................................................................................................................................................... 54
Figure 19. Recommended Reset Circuit.............................................................................................................................. 55
Figure 20. Recommended Reset Circuit for interfacing with CPU/FPGA Reset Output...................................................... 55
Figure 21. Reference Circuits for LED Strapping Pins......................................................................................................... 56
Figure 22. 25MHz Crystal / Oscillator Reference Clock Connection ................................................................................... 57
Figure 23. 50MHz Oscillator Reference Clock Connection ................................................................................................. 58
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