參數(shù)資料
型號: KSZ8051MLL-EVAL
廠商: Micrel Inc
文件頁數(shù): 4/48頁
文件大?。?/td> 0K
描述: BOARD EVALUATION FOR KSZ8051MLL
標(biāo)準(zhǔn)包裝: 1
主要目的: 接口,以太網(wǎng) PHY
嵌入式:
已用 IC / 零件: KSZ8051MLL
已供物品:
相關(guān)產(chǎn)品: 576-3888-6-ND - TXRX PHY 10/T100 3.3V MII 48LQFP
576-3888-1-ND - TXRX PHY 10/T100 3.3V MII 48LQFP
576-3888-2-ND - TXRX PHY 10/T100 3.3V MII 48LQFP
KSZ8051MLL TR-ND - TXRX PHY 10/T100 3.3V MII 48LQFP
576-3731-ND - TXRX PHY 10/T100 3.3V MII 48LQFP
其它名稱: 576-3864
Micrel, Inc.
KSZ8051MLL
July 2010
12
M9999-071210-1.0
Pin Description – KSZ8051MLL (Continued)
Pin Number
Pin Name
Type
(1)
Pin Function
47
RST#
I
Chip Reset (active low)
48
NC
-
No connect
Notes:
1.
P = Power supply.
Gnd = Ground.
I = Input.
O = Output.
I/O = Bi-directional.
Ipu/O = Input with internal pull-up (see Electrical Characteristics for value) during power-up/reset; output pin otherwise.
Ipd/O = Input with internal pull-down (see Electrical Characteristics for value) during power-up/reset; output pin otherwise.
Ipu/Opu = Input with internal pull-up (see Electrical Characteristics for value) during power-up/reset; output pin with internal pull-up (see
Electrical Characteristics for value) otherwise.
2.
MII Rx Mode: The RXD[3:0] bits are synchronous with RXC. When RXDV is asserted, RXD[3:0] presents valid data to the MAC. RXD[3:0] is
invalid data from the PHY when RXDV is de-asserted.
3.
MII Tx Mode: The TXD[3:0] bits are synchronous with TXC. When TXEN is asserted, TXD[3:0] presents valid data from the MAC. TXD[3:0]
has no effect on the PHY when TXEN is de-asserted.
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