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參數(shù)資料
| 型號： | KSZ8001L-EVAL |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 7/46頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR KSZ8001L |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 接口，以太網(wǎng) PHY |
| 嵌入式： | 否 |
| 已用 IC / 零件： | KSZ8001L |
| 主要屬性： | 單芯片 PHY，100BASE-TX/100BASE-FX/10BASE-T |
| 次要屬性： | MII，RMII，SMII，HP 自動 MDI，MDI-X 自動極性校正，LinkMD |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | KSZ8001SA3-ND - TXRX 10/100 LINKMD 3.3V 48-SSOP KSZ8001LIA3-ND - TXRX 10/100 LINKMD 3.3V 48-LQFP KSZ8001LA3TR-ND - TXRX 10/100 LINKMD 3.3V 48-LQFP KSZ8001LA3-ND - TXRX 10/100 LINKMD 3.3V 48-LQFP KSZ8001LA2TR-ND - TXRX 10/100 LINKMD 3.3V 48-LQFP KSZ8001LA2-ND - TXRX 10/100 LINKMD 3.3V 48-LQFP KSZ8001SL TR-ND - TXRX 10/100 LINKMD 3.3V 48-SSOP 576-2110-ND - TXRX 10/100 LINKMD 3.3V 48-SSOP KSZ8001SI-ND - TXRX 10/100 LINKMD 3.3V 48-SSOP KSZ8001S TR-ND - TXRX 10/100 LINKMD 3.3V 48-SSOP 更多... |
| 其它名稱： | 576-1620 |
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Micrel
KSZ8001
June 2009
Revision 1.04
15
Reference Clock (REF_CLK)
REF_CLK is a continuous 50 MHz clock that provides the timing reference for CRS_DV, RXD[1:0], TX_EN, TXD[1:0], and RX_ER.
REF_CLK is sourced by the MAC or an external source. Switch implementations may choose to provide REF_CLK as an input or an
output depending on whether they provide a REF_CLK output or rely on an external clock distribution device. Each PHY device shall
have an input corresponding to this clock but may use a single clock input for multiple PHYs implemented on a single IC.
Carrier Sense/Receive Data Valid (CRS_DV)
CRS_DV is asserted asynchronously on detection of carrier due to the criteria relevant to the operating mode. That is, in 10BASE-T
mode, when squelch is passed or in 100BASE-X mode when 2 non-contiguous zeroes in 10 bits are detected carrier is said to be
detected.
Loss of carrier shall result in the de-assertion of CRS_DV synchronous to REF_CLK. So long as carrier criteria are being met,
CRS_DV shall remain asserted continuously from the first recovered di-bit of the frame through the final recovered di-bit and shall be
negated prior to the first REF_CLK that follows the final di-bit.
The data on RXD[1:0] is considered valid once CRS_DV is asserted. However, since the assertion of CRS_DV is asynchronous
relative to REF_CLK, the data on RXD[1:0] shall be "00" until proper receive signal decoding takes place (see definition of RXD[1:0]
behavior).
Receive Data [1:0] (RXD[1:0])
RXD[1:0] shall transition synchronously to REF_CLK. For each clock period in which CRS_DV is asserted, RXD[1:0] transfers two
bits of recovered data from the PHY. In some cases (e.g. before data recovery or during error conditions) a pre-determined value for
RXD[1:0] is transferred instead of recovered data. RXD[1:0] shall be "00" to indicate idle when CRS_DV is de-asserted. Values of
RXD[1:0] other than "00" when CRS_DV is de-asserted are reserved for out-of-band signaling (to be defined). Values other than "00"
on RXD[1:0] while CRS_DV is de-asserted shall be ignored by the MAC/repeater. Upon assertion of CRS_DV, the PHY shall ensure
that RXD[1:0]=00 until proper receive decoding takes place.
Transmit Enable (TX_EN)
Transmit Enable TX_EN indicates that the MAC is presenting di-bits on TXD[1:0] on the RMII for trans-mission. TX_EN shall be
asserted synchronously with the first nibble of the preamble and shall remain asserted while all di-bits to be transmitted are
presented to the RMII. TX_EN shall be negated prior to the first REF_CLK following the final di-bit of a frame. TX_EN shall transition
synchronously with respect to REF_CLK.
Transmit Data [1:0] (TXD[1:0])
Transmit Data TXD[1:0] shall transition synchronously with respect to REF_CLK. When TX_EN is asserted, TXD[1:0] are accepted
for transmission by the PHY. TXD[1:0] shall be "00" to indicate idle when TX_EN is de-asserted. Values of TXD[1:0] other than "00"
when TX_EN is de-asserted are reserved for out-of-band signaling (to be defined). Values other than "00" on TXD[1:0] while TX_EN
is disserted shall be ignored by the PHY.
Collision Detection
Since the definition of CRS_DV and TX_EN both contain an accurate indication of the start of frame, the MAC can reliably
regenerate the COL signal of the MII by Ending TX_EN and CRS_DV.
During the IPG time following the successful transmission of a frame, the COL signal is asserted by some transceivers as a self-test.
The Signal Quality Error (SQE) function will not be supported by the reduced MII due to the lack of the COL signal. Historically, SQE
was present to indicate that a transceiver located physically remote from the MAC was functioning. Since the reduced MII only
supports chip-to-chip connections on a PCB, SQE functionality is not required.
RX_ER
The PHY shall provide RX_ER as an output according to the rules specified in IEEE 802.3u [2] (see Clause 24, Figure 24-11 -
Receive State Diagram). RX_ER shall be asserted for one or more REF_CLK periods to indicate that an error (e.g. a coding error or
any error that a PHY is capable of detecting, and that may otherwise be undetectable by the MAC sublayer) was detected
somewhere in the frame presently being transferred from the PHY. RX_ER shall transition synchronously with respect to REF_CLK.
While CRS_DV is de-asserted, RX_ER shall have no effect on the MAC.
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| KSZ8001LI | 功能描述:以太網(wǎng) IC 10/100 BASE-TX/FX Physical Layer Transceiver with LinkMD cable diagnostics, Single 3.3V Supply, 48-LQFP, Lead Free RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| KSZ8001LI TR | 功能描述:以太網(wǎng) IC 10/100 BASE-TX/FX Physical Layer Transceiver with LinkMD cable diagnostics, Single 3.3V Supply, 48-LQFP, I-Temp, Lead Free RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| KSZ8001LIA3 | 功能描述:TXRX 10/100 LINKMD 3.3V 48-LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:1,140 系列:AU 類型:收發(fā)器 驅(qū)動器/接收器數(shù):1/1 規(guī)程:CAN 電源電壓:5.3 V ~ 27 V 安裝類型:表面貼裝 封裝/外殼:14-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:14-SO 包裝:管件 其它名稱:935267940512AU5790D14AU5790D14-ND |
| KSZ8001S | 功能描述:以太網(wǎng) IC 10/100 BASE-TX/FX Physical Layer Transceiver with LinkMD cable diagnostics, Single 3.3V Supply, 48-SSOP, Lead Free RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| KSZ8001S TR | 功能描述:以太網(wǎng) IC 10/100 BASE-TX/FX Physical Layer Transceiver with LinkMD cable diagnostics, Single 3.3V Supply, 48-SSOP, Lead Free RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
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