
Micrel, Inc.
KS8997/KSZ8997
February 2007
20
M9999-022807-1.1
The table below briefly summarizes priority features. For more detailed settings see “EEPROM Memory Map”
section.
Register(s)
Bit(s)
Global/Port
Description
General
2
3-2
Global
Priority Control Scheme: Transmit buffer high/low interleave control
2
1
Global
Priority Buffer Reserve: Reserves 6KB of the buffer for high priority traffic
4-11
0
Port
Enable Port Queue Split: Splits the transmit queue on the desired port for high
and low priority traffic
DSCP Priority
4-11
5
Port
Enable Port DSC: Looks at DSCP field in IP header to decide high or low priority
40-47
7-0
Global
DSCP Priority Points: Fully decoded 64-bit register used to determine priority
from DSCP field (6 bits) in the IP header
802.1p Priority
4-11
4
Port
Enable Port 802.1p Priority: Uses the 802.1p priority tag (3 bits) to determine
frame priority
3
7-0
Global
Priority Classification: Determines which tag values have high priority
Per Port Priority
4-11
3
Port
Enable Port Priority: Determines which ports have high priority traffic
Table 1. Priority Control
VLAN Operation
The VLAN’s are setup by programming the VLAN Mask Registers in the “EEPROM Memory Map” section. The
perspective of the VLAN is from the input port and which output ports it sees directly through the switch. For example
if port 1 only participated in a VLAN with ports 2 and 8 then one would set bits 0 and 6 in register 13 (Port 1 VLAN
Mask Register). Note that different ports can be setup independently. An example of this would be where a router is
connected to port 8 and each of the other ports would work autonomously. In this configuration ports 1 through 7
would only set the mask for port 8 and port 8 would set the mask for ports 1 through 7. In this way the router could
see all ports and each of the other individual ports would only communicate with the router.
All multicast and broadcast frames adhere to the VLAN configuration. Unicast frame treatment is a function of
register 2 bit 0. If this bit is set then unicast frames only see ports within their VLAN. If this bit is cleared unicast
frames can traverse VLAN’s.
VLAN tags can be added or removed on a per port basis. Further, there are provisions to specify the tag value to be
inserted on a per port basis.
The table below briefly summarizes VLAN features. For more detailed settings see “EEPROM Memory Map” section.
Register(s)
Bit(s)
Global/Port
Description
4-11
2
Port
Insert VLAN Tags: If specified, will add VLAN tags to frames without existing tags
4-11
1
Port
Strip VLAN Tags: If specified, will remove VLAN tags from frames if they exist
2
0
Global
VLAN Enforcement: Allows unicast frames to adhere or ignore the VLAN configuration
13-20
7-0
Port
VLAN Mask Registers: Allows configuration of individual VLAN grouping
22-38
7-0
Port
VLAN Tag Insertion Values: Specifies the VLAN tag to be inserted if enabled (see
above)
Table 2. VLAN Control