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參數(shù)資料
| 型號(hào)： | KS88C9408 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 8-Bit CMOS Microcontroller(8位 CMOS 微控制器) |
| 中文描述： | 8位CMOS微控制器（8位的CMOS微控制器） |
| 文件頁(yè)數(shù)： | 4/12頁(yè) |
| 文件大?。?/td> | 73K |
| 代理商： | KS88C9408 |
KS88C9408
PRELIMINARY DATA SHEET
4
FUNCTION OVERVIEW
CPU
The KS88C9408 8-bit CPU (SAM87) architecture is
based on a 16-bit address bus and an 8-bit data bus.
The internal bus supports memory, register, and
stack operations, interrupt handling, clock, and
power-down control logic.
Instruction Set
The SAM87 instruction set is designed to support a
large register file and consists of 78 instructions,
including multiply and divide.
The instruction set also supports decimal adjustment
of binary-coded decimal (BCD) numbers, 16-bit word
increment and decrement, and bit addressing, as
well as rotate and shift operations.
Addressing Modes
The KS88C9408 register architecture uses an
efficient method of working register addressing to
take full advantage of shorter instruction formats and
to reduce execution times. An instruction can
address a single 8-bit register or a 16-bit register
pair. There are seven explicit addressing modes (not
all addressing modes are available for each
instruction):
— Register (R)
— Indirect Register (IR)
— Indexed (X)
— Direct Address (DA)
— Indirect Address (IA)
— Relative Address (RA)
— Immediate (IM)
Interrupts
The SAM87 interrupt structure has three
components: level, source, and vector. The
KS88C9408 uses one interrupt source and one
vector (one vector for one source).
Interrupt source corresponds to one level. One
interrupt level can be selected for the special fast
interrupt processing feature.
System Clock Control
Clock frequency input from an external device may
range from 1–5 MHz. The typical input clock
frequency is 3.57 MHz. To obtain this frequency, you
must select a non-divided CPU clock using the
appropriate system clock control register settings.
Please note that the data transfer rates which are
supported by the KS88C9408 serial I/O interface
(9.6, 19.2, and 38.4 Kbps) are based on the typical
3.57-MHz clock frequency value.
Basic Timer
The KS88C9408 8-bit basic timer has two functions:
— To provide an automatic reset mechanism
(watchdog timer function) in the event of a
system malfunction. If the 8-bit counter
overflows, a system reset is initiated.
— To determine the length of the oscillation
stabilization interval following a reset. When an
external reset or interrupt occurs in Stop mode,
or when a power-on reset occurs, the CPU waits
for the reset release interval to elapse before
resuming normal operation.
Reset Operations
When the power supplied to the KS88C9408 through
the V
DD
pin reaches a minimum level, an internal
reset operation is initiated. A reset can also be
triggered by the rising edge of the external reset
signal through the RST pin.
The minimum Low level width of the external reset
signal is 5 μs. An overflow of the basic timer counter
signals the CPU that the programmed oscillation
stabilization interval has elapsed, and that it can
enter normal operating mode.
The KS88C9408 has an integrated power-on reset
circuit. When RESET is released and returns to High
level, the CPU fetches the instruction stored at
program memory location 100H (the reset vector
address), and then jumps to the start address of the
application program (400H).
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