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參數(shù)資料
| 型號(hào)： | KS88C0316 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 8-Bit CMOS Microcontroller(8位 CMOS 微控制器) |
| 中文描述： | 8位CMOS微控制器（8位的CMOS微控制器） |
| 文件頁(yè)數(shù)： | 6/7頁(yè) |
| 文件大小： | 29K |
| 代理商： | KS88C0316 |
P0.0–P0.7
I/O
Nibble-addressable I/O port for Schmitt
trigger input or push-pull output. N-channel,
open-drain, output mode and pull-up
resistors are assignable by software. Port 0
can also be configured as external interface
address lines A8–A15.
Same general characteristics as port 0.
Port 1 can alternatively be used as external
interface address/data lines AD0–AD7.
I/O port for Schmitt trigger input or push-
pull output. P2.0–P2.3 can be configured for
external bus control signals. Upper nibble
pins P2.4–P2.7 are bit-programmable for
external interrupts INT0–INT3. P2.4 can be
used as a
WAIT
signal input for the
external interface.
I/O port with bit-programmable pins;
Schmitt trigger input or push-pull output.
Each port 3 pin has an alternative function:
P3.0: TCCK (timer C clock input)
P3.1: TDCK (timer D clock input)
P3.2: ARxD (ADLC receiver data input)
P3.3: ATxD (ADLC transmitter data output)
P3.4: TA (timer A output)
P3.5: TB (timer B output)
P3.6: TxD (UART transmit)
P3.7: RxD (UART receive)
(ADLC and UART pins are multiplexed.)
Bit-addressable I/O port for Schmitt trigger
input or push-pull output. Pull-up resistors
are software-assignable. Alternate functions
include external interrupt inputs INT4–
INT11 (with interrupt enable and pending
control) and the timer C and timer D gate
inputs at P4.0 and P4.1, respectively.
Nibble-addressable I/O port for Schmitt
trigger input or push-pull output. N-channel,
open-drain, output mode and pull-ups are
assignable by software. P5.4 and P5.5 are
alternatively used as ADLC receiver and
transmitter clock input pins, respectively.
(The ADLC control pins are multiplexed.)
N-channel, open-drain output port with up to
9-volt load capacity
System clock input and output pins
6
8–1
A8–A15
P1.0–P1.7
I/O
6
63–56
AD0–AD7
P2.0–P2.3
P2.4–P2.7
I/O
5 (lower
nibble);
4 (upper
nibble; with
noise filter)
42–39;
38–35
AS
,
DS
,
DM
, R/
W
;
INT0–INT3,
WAIT
P3.0–P3.7
I/O
5
25–18
(See pin
description)
P4.0–P4.7
I/O
3
(with
noise filter)
16–9
INT4–
INT11;
TCG, TDG
P5.0–P5.5
I/O
6
44–49
ARxC
ATxC
P6.0–P6.7
O
2
26–31,
33–34
50, 51
–
X
IN
, X
OUT
XT
IN
, XT
OUT
–
–
–
–
Sub-oscillator clock pins for backup timer
–
53, 54
–
Table 1. KS88C0316 Pin Descriptions (Continued)
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