參數(shù)資料
型號(hào): KS86P6008
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 8-Bit CMOS Microcontroller(8位微控制器)
中文描述: 8位CMOS微控制器(8位微控制器)
文件頁(yè)數(shù): 6/7頁(yè)
文件大小: 48K
代理商: KS86P6008
PRODUCT OVERVIEW
KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec)
1-6
PIN DESCRIPTIONS
Table 1-1. KS86C6004/C6008/P6008 Pin Descriptions
Pin
Names
P0.0-P0.7
Pin
Type
I/O
Pin
Description
Circuit
Number
B
Pin
Numbers
36–29
(30–23)
Share
Pins
INT2
Bit-programmable I/O port for Schmitt trigger
input or open-drain output. Port0 can be
individually configured as external interrupt
inputs. Pull-up resistors are assignable by
software.
Bit-programmable I/O port for Schmitt trigger
input or open-drain output. Pull-up resistors are
assignable by software.
Bit-programmable I/O port for Schmitt trigger
input or open-drain output. Port2 can be
individually configured as external interrupt
inputs. Pull-up resistors are assignable by
software.
Bit-programmable I/O port for Schmitt trigger
input, open-drain or push-pull output. P3.3 can
be used to system clock output(CLO) pin.
Bit-programmable I/O port for Schmitt trigger
input or open-drain output or push-pull output.
Port4 can be individually configured as external
interrupt inputs. In output mode, pull-up resistors
are assignable by software. But in input mode,
pull-up resistors are fixed.
Only be used USB tranceive/receive port; D+/D-.
3.3 V output from internal voltage regulator
System clock input and output pin
(crystal/ceramic oscillator, or external clock
source)
External interrupt for bit-programmable port0,
port2 and port4 pins when set to input mode.
P1.0-P1.7
I/O
B
28–21
(22–15)
P2.0-P2.7
I/O
B
3–10
(41–44, 1–4)
INT0
P3.0-P3.3
I/O
C
2, 1, 42, 41
(40–37)
P3.3/CLO
P4.0-P4.3
I/O
D
16, 17, 19, 20
(10, 11, 13,
14)
INT1
D+/D-
3.3 V
OUT
X
IN
, X
OUT
I/O
40–39 (36-35)
38 (34)
14, 13
(8, 7)
INT0
INT1
INT2
I
3–10, 16,17,
19, 20, 29–36
(30–23, 41–
44, 1–4, 10,
11, 13, 14)
18 (12)
PORT2/
PORT4/
PORT0
RESET
I
RESET
signal input pin. Schmitt trigger input with
internal pull-up resistor.
Test signal input pin (for factory use only; must
be connected to V
SS
)
Power input pin
Vss1 is a ground power for CPU core.
Vss2 is a ground power for I/O and OSC block.
No connection
A
TEST
I
15 (9)
V
DD
V
SS1,
V
SS2
11 (5)
12, 37
(6, 31)
(32, 33)
NC
NOTE
: Pin numbers shown in parenthesis '( )' are for the 44-QFP package; others are for the 42-SDIP package.
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