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參數(shù)資料
| 型號(hào)： | KS57P21408 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 4-BIT CMOS Microcontroller(4位微控制器) |
| 中文描述： | 4位CMOS微控制器（4位微控制器） |
| 文件頁(yè)數(shù)： | 5/6頁(yè) |
| 文件大小： | 38K |
| 代理商： | KS57P21408 |
KS57C21408/P21408 MICROCONTROLLER
PRODUCT OVERVIEW
1-
5
PIN DESCRIPTIONS
Table 1-1. Pin Descriptions
Pin Name
Pin
Type
I
Description
Circuit
Type
A-1
Pin
Number
35–32
Share Pin
P0.0 – P0.3
4-bit input port.
1 or 4-bit read/test possible.
Pull-up register.
2-bit Input port.
1 or 2-bit read/test is possible, 2-bit unit pull-up
resistor selectable by software.
2-bit I/O port. 1 or 2-bit read/write/test is possible.
Each individual pin can be specified as input or
output.
2-bit unit pull-up resistors selectable by software.
Pull-up resistors are automatically disabled for
output pins.
4-bit I/O port. 1, 4 or 8-bit read/write/test possible.
4-pin unit can be specified as input or output.
4-bit unit pull-up resistors are selectable by
software. Pull-up resistors are automatically
disabled for output pins.
Individual pins are software configurable as open-
drain or push-pull output.
4-bit I/O port. 1, 4 or 8-bit read/write/test possible.
Each individual pin can be specified as input or
output.
4-bit unit pull-up resistors selectable by software.
Pull-up resistors are automatically disabled for
output pins.
4-bit I/O port. 1, 4 or 8-bit read/write/test possible.
4-pin unit can be specified as input or output.
4-bit unit pull-up resistors are selectable by
software. Pull-up resistors are automatically
disabled for output pins.
4-bit controllable output.
(Dual function as segment output pins)
LCD segment display signal output.
K0–K3
P1.0
P1.1
I
A-3
37
36
INT0
INT1
P2.0
P2.1
I/O
D
23
24
BUZ
CLO
P4.0
P4.1
P4.2
P5.0–P5.3
I/O
E
E-1
E
29
30
31
25–28
TCL0
TCLO0
P6.0 – P6.3
I/O
D-1
7–10
KS0 – KS3
P7.0 – P7.3
11–14
KS4 – KS7
P8.0 – P8.15
O
H-9
42–57
SEG0 –
SEG15
–
SEG16–
SEG59
SEG0 –
SEG15
COM0 – COM8
H-10
58–100
,1
42–57
LCD segment display signal output.
H-9
P8.0 – P8.15
LCD common signal output.
H-11
38–41
2–6
37–36
7–14
35–32
–
INT0 – INT1
KS0 – KS7
K0 – K3
I
Rising or falling edge detection selectable.
Quasi-interrupt input for falling edge detection.
Vector interrupt input
K0 – K3: falling edge detection
P1.0 –P1.1
P6.0 – P7.3
P0.0 – P0.3
I/O
I
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