參數(shù)資料
型號: KS16114
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 9600/14400 bps FAX MODEM
中文描述: 14400分之9600基點傳真調(diào)制解調(diào)器
文件頁數(shù): 37/69頁
文件大?。?/td> 513K
代理商: KS16114
KS16112/4
9600/14400 bps FAX MODEM
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37
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3.3 DSP RAM Read Procedure
The RAM read procedure is a 32 - bit transfer from the DSP RAM to the interface memory. Both the X
and Y RAM data is transferred simultaneously. The sequence of events is as follows:
Before accessing the DSP interface memory, first reset RA1 and/or RA2, then reset BDA1 and/or BDA2
by reading YDL1 and/or YDL2.
Reset WT1 and/or WT2 to instruct the modem that a RAM read operation will take place when RA1
and/or RA2 is set.
Load the RAM address into ADR1 and/or ADR2 and then set CRAM
X
and BRT
X
to desired values,
where x = 1 or 2
Set RA1 and/or RA2 to instruct the modem to perform the RAM read operation.
BDA1 and/or BDA2 will be set when the modem has completed the transfer from the DSP RAM to the
interface memory RAM data registers.
When the modem sets BDA1 and/or BDA2, IRQ is also asserted if INTE1 and/or INTE2 is set.
INTA1 and/or INTA2 is set to inform the host that BDA1 and/or BDA2 was the source of the interrupt.
In the order listed, read XDM1, XDL1, YDM1, and YDL1; and/or XDM2, XDL2, YDM2, and YDL2. Reading
YDL1 resets INTA1 and BDA1 and/or reading YDL2 resets INTA2 and BDA2 causing IRQ to go inactive
if no other interrupts are pending.
The DSP RAM write procedure is a 16 - bit transfer from the interface memory to the DSP RAM. Thus
X RAM data or Y RAM data can be transferred each baud or sample time. The sequence of events is
as follows :
3.4 DSP RAM Write Procedure
Before writing to the DSP interface memory, first reset RA1 and/or RA2 and then reset BDA1 and/or
BDA2 by reading YDL1 and/or YDL2, respectively.
Write the RAM address into ADR1 and/or ADR2 and then set CRAM1 and BRT1 and/or CRAM2 and
BRT2 to the desired values.
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