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參數(shù)資料
| 型號： | KS0708 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 64COM/128SEG DRIVE FOR DOT MATRIX LCD |
| 中文描述： | 64COM/128SEG驅(qū)動的點(diǎn)陣LCD |
| 文件頁數(shù)： | 14/27頁 |
| 文件大小： | 212K |
| 代理商： | KS0708 |
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PRELIMINARY SPECIFICATION
64COM/128SEG DRIVE FOR DOT MATRIX LCD
KS0708
14
M/M-96-D001
97-09-19
Data Tramsfer
To match the timing of the display data RAM and registers to that of the controlling microprocessor,
KS0708 uses an internal data bus and bus buffer. When the microprocessor reads the contents of display
data RAM, the data for the initial read cycle is first stored inthe bus buffer (dummy read cycle). On the next
read cycle, the data is read from the bus buffer onto the microprocessor bus. At the same time, the next
block of data is transferred from RAM to the bus buffer. Otherwise, when the microprocessor write data to
display data RAM. the data is written to RAM atfer the falling edge of
￡à
E
￡§
. Therefore, it is necessary to
check Busy Flag to write or read the next data. (refer to Figure4, 5)
Page Address Register
The 3-bit Page Address register provides the page address to display data RAM (refer to Figure 3). The
microprocessor issues Set Page Address instruction to change the page and to access another page.
Column Address Counter
The column address counter is a 6-bit presettable counter that provides column address to display data
RAM (refer to Figure 3). It is incremented by 1 automatically after execution of each Read/Write Data
instruction. The column address counter loops the values 0 to 127, and it is independent of page address
register. The ADC pin is issued to change the relationship between RAM Column address and display seg-
ment output.
Display Start Line Register
The display start line register stores the line address of display data RAM that corresponds to the first (nor-
mally the top) line(COM1) of liquid crystal display(LCD) panel. See Figure 3. When displaying contents in
display data RAM on the LCD panel, 6-bit data(DB[5:0]) of the Set Display Start Line is latched in display
start line register. Latched data are transferred to the line address counter just before COM1 is active High,
presetting the line address counter. The line counter is then incremented on the display latch clock signal
once for every display line. It is used for vertical scrolling of the liquid crystal display screen.
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| KS0741 | 128 SEG / 129 COM DRIVER & CONTROLLER FOR 4 GRAY SCALE STN LCD |
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相關(guān)代理商/技術(shù)參數(shù) |
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| KS0713 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD |
| KS0715 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD |
| KS0717 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:55 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD |
| KS0718 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:81 COM / 104 SEG DRIVER & CONTROLLER FOR STN LCD |
| KS0724 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD |
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