參數(shù)資料
型號: KS0118C
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: GENLOCK ADC(采樣時鐘鎖定的視頻/數(shù)字轉換器)
中文描述: 鎖相模數(shù)轉換器(采樣時鐘鎖定的視頻/數(shù)字轉換器)
文件頁數(shù): 9/12頁
文件大?。?/td> 113K
代理商: KS0118C
GENLOCK ADC
KS0118C
9
FUNCTION DESCRIPTION
GENERAL DESCRIPTION
The KS0118C implements the funtions of an 8-Bit
ADC, Analog Clamp, Analog PLL Clock Generator and Digital
Timing Generation. Through the use of VLSl technology, the KS0118C combines analog circuits with digital signal
processing to obtain locking characteristics not achievable by ordinary methods. The KS0118C uses one external
frequency reference to create many different programmable line-lock sampling clocks.
ANALOG TO DIGITAL CONVERTER
The KS0118C uses a two step, 8-bit and auto zero ADC to digitize the analog video input. The VRT and VRB pins
are the top and bottom reference voltage for the ADC. These references are generated internally but requires
0.1
μ
F decoupling capacitors to ground.
EXTERNAL FREQUENCY REFERENCE
The KS0118C requires an external stable frequency reference to generate the sampling clock. Although a wide
range of frequency will work with the GENLOCK, it is recommended that 24.576 MHz be used as the reference.
This can be derived from a standard crystal or an external clock.
ANALOG PHASE LOCK LOOP
The KS0118C has an internal PLL used for producing the sampling clock. This PLL requires an external loop filter
at pin 1 (RCPLL) as shown in the application circuit. The ground connections for this filter should be placed close to
pin 78, while the inputs should be located close to pin 1. The PLL also requires an external resistor to convert the
voltage of the RCPLL node to a current for use by the internal VCO. The voltage of pin 76 (RVCO) will track
RCPLL, although the absolute voltage of these pins depends on many factors, it will be between 0.75 and 4.50V.
The voltage will exhibit the standard characteristics of an analog PLL.
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