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參數(shù)資料
| 型號(hào)： | KMPC870ZT133 |
| 廠商： | Freescale Semiconductor |
| 文件頁(yè)數(shù)： | 8/84頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU POWERQUICC 133MHZ 256PBGA |
| 標(biāo)準(zhǔn)包裝： | 2 |
| 系列： | MPC8xx |
| 處理器類(lèi)型： | 32-位 MPC8xx PowerQUICC |
| 速度： | 133MHz |
| 電壓： | 3.3V |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 256-BGA |
| 供應(yīng)商設(shè)備封裝： | 256-PBGA（23x23） |
| 包裝： | 托盤(pán) |
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MPC875/MPC870 PowerQUICC Hardware Specifications, Rev. 4
16
Freescale Semiconductor
Layout Practices
10 Layout Practices
Each VDD pin on the MPC875/MPC870 should be provided with a low-impedance path to the board’s
supply. Each GND pin should likewise be provided with a low-impedance path to ground. The power
supply pins drive distinct groups of logic on chip. The V
DD power supply should be bypassed to ground
using at least four 0.1-F bypass capacitors located as close as possible to the four sides of the package.
Each board designed should be characterized and additional appropriate decoupling capacitors should be
used if required. The capacitor leads and associated printed-circuit traces connecting to chip VDD and
GND should be kept to less than half an inch per capacitor lead. At a minimum, a four-layer board
employing two inner layers as VDD and GND planes should be used.
All output pins on the MPC875/MPC870 have fast rise and fall times. Printed circuit (PC) trace
interconnection length should be minimized in order to minimize undershoot and reflections caused by
these fast output switching times. This recommendation particularly applies to the address and data buses.
Maximum PC trace lengths of 6 inches are recommended. Capacitance calculations should consider all
device loads as well as parasitic capacitances due to the PC traces. Attention to proper PCB layout and
bypassing becomes especially critical in systems with higher capacitive loads because these loads create
higher transient currents in the VDD and GND circuits. Pull up all unused inputs or signals that will be
inputs during reset. Special care should be taken to minimize the noise levels on the PLL supply pins. For
more information, refer to Section 14.4.3, “Clock Synthesizer Power (VDDSYN, VSSSYN, VSSSYN1),” in
the MPC885 PowerQUICC Family Reference Manual.
PADIR (Port A data direction register)
PADIR[5:9]
PADIR[12:13]
0
PBPAR (Port B pin assignment register)
PBPAR[14:18]
PBPAR[20:22]
0
PBDIR (Port B data direction register)
PBDIR[14:8]
PBDIR[20:22]
0
PCPAR (Port C pin assignment register)
PCPAR[4:5]
PCPAR[8:9]
PCPAR[14]
0
PCDIR (Port C data direction register)
PCDIR[4:5]
PCDIR[8:9]
PCDIR[14]
0
PDPAR (Port D pin assignment register)
PDPAR[3:7]
PDPAR[9:5]
0
PDDIR (Port D data direction register)
PDDIR[3:7]
PDDIR[9:15]
0
Table 7. Mandatory Reset Configuration of MPC875/MPC870 (continued)
Register/Configuration
Field
Value
(Binary)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| KMPC870ZT66 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Hardware Specifications |
| KMPC870ZT80 | 功能描述:微處理器 - MPU PQ I HIP6W DUET RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類(lèi)型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| KMPC875 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Hardware Specifications |
| KMPC875CVR133 | 功能描述:微處理器 - MPU PQ I HIP6W DUET RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類(lèi)型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| KMPC875CVR66 | 功能描述:微處理器 - MPU PQ I HIP6W DUET RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類(lèi)型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
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