參數(shù)資料
型號: KMPC855TCZQ50D4
廠商: Freescale Semiconductor
文件頁數(shù): 66/78頁
文件大小: 0K
描述: IC MPU POWERQUICC 50MHZ 357-PBGA
標(biāo)準(zhǔn)包裝: 2
系列: MPC8xx
處理器類型: 32-位 MPC8xx PowerQUICC
速度: 50MHz
電壓: 3.3V
安裝類型: 表面貼裝
封裝/外殼: 357-BBGA
供應(yīng)商設(shè)備封裝: 357-PBGA(25x25)
包裝: 托盤
MPC860 PowerQUICC Family Hardware Specifications, Rev. 9
Freescale Semiconductor
69
FEC Electrical Characteristics
13.3
MII Async Inputs Signal Timing (MII_CRS, MII_COL)
Table 31 provides information on the MII async inputs signal timing.
Figure 74 shows the MII asynchronous inputs signal timing diagram.
Figure 74. MII Async Inputs Timing Diagram
13.4
MII Serial Management Channel Timing (MII_MDIO, MII_MDC)
Table 32 provides information on the MII serial management channel signal timing. The FEC functions
correctly with a maximum MDC frequency in excess of 2.5 MHz. The exact upper bound is under
investigation.
Table 31. MII Async Inputs Signal Timing
Num
Characteristic
Min
Max
Unit
M9
MII_CRS, MII_COL minimum pulse width
1.5
MII_TX_CLK
period
Table 32. MII Serial Management Channel Timing
Num
Characteristic
Min
Max
Unit
M10
MII_MDC falling edge to MII_MDIO output invalid (minimum propagation
delay)
0—
ns
M11
MII_MDC falling edge to MII_MDIO output valid (max prop delay)
25
ns
M12
MII_MDIO (input) to MII_MDC rising edge setup
10
ns
M13
MII_MDIO (input) to MII_MDC rising edge hold
0
ns
M14
MII_MDC pulse width high
40%
60%
MII_MDC
period
M15
MII_MDC pulse width low
40%
60%
MII_MDC
period
MII_CRS, MII_COL
M9
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