參數(shù)資料
型號(hào)： KMPC8540VT667LC
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 5/24頁(yè)
文件大小： 0K
描述： IC MPU PWRQUICC 783-FCPBGA
標(biāo)準(zhǔn)包裝： 2
系列： MPC85xx
處理器類(lèi)型： 32-位 MPC85xx PowerQUICC III
速度： 667MHz
電壓： 1.2V
安裝類(lèi)型： 表面貼裝
封裝/外殼： 784-BBGA，F(xiàn)CBGA
供應(yīng)商設(shè)備封裝： 783-FCPBGA（29x29）
包裝： 托盤(pán)
MPC8540 PowerQUICC III Integrated Host Processor Product Brief, Rev. 0.1
Freescale Semiconductor
13
MPC8540 Architecture Overview
3.5 Programmable Interrupt Controller (PIC)
The programmable interrupt controller (PIC) implements the necessary functions to provide a flexible solution for
a general-purpose interrupt control. The interrupt controller unit implements the logic and programming structures
of the OpenPIC architecture. The MPC8540 interrupt controller unit supports its processor core and provides for 12
external interrupts (with fully nested interrupt delivery), 4 message interrupts, internal-logic driven interrupts, and
4 global high resolution timers. Up to 16 programmable interrupt priority levels are supported.
The interrupt controller unit can be bypassed to allow use of an external interrupt controller. Inter-processor interrupt
(IPI) communication is supported through the external interrupt and core reset signals of different processor cores
on the same device. The four IPIs are only used for self-interrupt in a single-core device such as the MPC8540.
3.6 I2C Controller
The inter-IC (IIC or I2C) bus is a two-wire, bidirectional serial bus that provides a simple and efficient method of
data exchange between devices. The synchronous, multiple master bus of the I
2C allows the MPC8540 to exchange
data with other I
2C devices, such as microcontrollers, EEPROMs, real-time clock devices, A/D converters, and
LCDs. The two-wire bus (serial data SDA and serial clock SCL) minimizes the interconnections between devices.
The synchronous, multiple master bus of the I2C allows the connection of additional devices to the bus for expansion
and system development.
The I2C controller is a true multiple master bus; it includes collision detection and arbitration that prevents data
corruption if two or more masters attempt to control the bus simultaneously. This feature allows for complex
applications with multiprocessor control. The I
2C controller consists of a transmitter/receiver unit, a clocking unit,
and a control unit. The I2C unit supports general broadcast mode, and on-chip filtering rejects spikes on the bus.
3.7 Boot Sequencer
The MPC8540 provides a boot sequencer that uses the I2C interface to access an external serial ROM and loads the
data into the MPC8540’s configuration registers. The boot sequencer is enabled by a configuration pin sampled at
the negation of the MPC8540 hardware reset signal. If enabled, the boot sequencer holds the MPC8540 processor
core in reset until the boot sequence is complete. If the boot sequencer is not enabled, the processor core exits reset
and fetches boot code in default configurations.
3.8 Dual Universal Asynchronous Receiver/Transmitter (DUART)
The MPC8540 includes a DUART intended for use in maintenance, bringing-up, and debugging of systems. The
MPC8540 provides a standard four-wire handshake (SIN, SOUT, RTS, CTS) for each port. The DUART is a slave
interface. An interrupt is provided to the interrupt controller or optionally steered externally to allow device
handshakes. Interrupts are generated for transmit, receive, line status, and MODEM status.
The MPC8540 DUART supports full-duplex operation. It is compatible with the PC16450 and PC16550
programming models. Also, 16-byte FIFOs are supported for both the transmitter and the receiver.
Software programmable baud generators divide the system clock to generate a 16x clock. Serial interface data
formats (data length, parity, 1/1.5/2 STOP bit, baud rate) are also software selectable.
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