參數(shù)資料
型號: KMPC8540CPX667JB
廠商: Freescale Semiconductor
文件頁數(shù): 20/24頁
文件大?。?/td> 0K
描述: IC MPU PWRQUICC 783-FCPBGA
標準包裝: 2
系列: MPC85xx
處理器類型: 32-位 MPC85xx PowerQUICC III
速度: 667MHz
電壓: 1.2V
安裝類型: 表面貼裝
封裝/外殼: 784-BBGA,F(xiàn)CBGA
供應商設備封裝: 783-FCPBGA(29x29)
包裝: 托盤
MPC8540 PowerQUICC III Integrated Host Processor Product Brief, Rev. 0.1
Freescale Semiconductor
5
MPC8540 Overview
— On-chip digital filtering rejects spikes on the bus
Boot sequencer
— Optionally loads configuration data from serial ROM at reset through the I2C interface
— Can be used to initialize configuration registers and/or memory
— Supports extended I
2C addressing mode
— Data integrity checked with preamble signature and CRC
DUART
— Two 4-wire interfaces (SIN, SOUT, RTS, CTS)
— Programming model compatible with the original 16450 UART and the PC16550D
10/100 fast Ethernet controller (FEC)
— Operates at 10 to 100 megabits per second (Mbps) as a device debug and maintenance port
Local bus controller (LBC)
— Multiplexed 32-bit address and data operating at up to 166 MHz
— Eight chip selects support eight external slaves
— Four- and eight-beat burst transfers
— The 32-, 16-, and 8-bit port sizes are controlled by an on-chip memory controller.
— Three protocol engines available on a per chip select basis:
– General-purpose chip select machine (GPCM)
– Three user programmable machines (UPMs)
– Dedicated single data rate SDRAM controller
— Parity support
— Default boot ROM chip select with configurable bus width (8-,16-, or 32-bit)
Two three-speed (10/100/1Gb) Ethernet controllers (TSECs)
— Dual IEEE 802.3, 802.3u, 802.3x, 802.3z, 802.3ac, 802.3ab compliant controllers
— Support for different Ethernet physical interfaces:
– 10/100/1Gb IEEE 802.3 GMII
– 10/100 Mbps IEEE 802.3 MII
– 10-Mbps IEEE 802.3 MII
– 1-Gbps IEEE 802.3z TBI
– 10/100/1Gb RGMII/RTBI
— Full- and half-duplex support
— Buffer descriptors are backward compatible with MPC8260 and MPC860T 10/100 programming
models
— 9.6-Kbyte jumbo frame support
— RMON statistics support
— 2-Kbyte internal transmit and receive FIFOs
— MII management interface for control and status
— Programmable CRC generation and checking
— Ability to force allocation of header information and buffer descriptors into L2 cache
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