controller, dual I
參數(shù)資料
型號: KMPC8379ECVRALG
廠商: Freescale Semiconductor
文件頁數(shù): 30/117頁
文件大?。?/td> 0K
描述: IC MPU POWERQUICC II 689-PBGA
標準包裝: 2
系列: MPC83xx
處理器類型: 32-位 MPC83xx PowerQUICC II Pro
速度: 667MHz
電壓: 1V
安裝類型: 表面貼裝
封裝/外殼: 689-BBGA 裸露焊盤
供應商設備封裝: 689-TEPBGA II(31x31)
包裝: 托盤
MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
2
Freescale Semiconductor
controller, dual I2C controllers, a 4-channel DMA controller, an enhanced secured digital host controller,
and a general-purpose I/O port. This figure shows the block diagram of the chip.
Figure 1. MPC8379E Block Diagram and Features
The following features are supported in the chip:
e300c4s core built on Power Architecture technology with 32 KB instruction cache and 32 KB
data cache, a floating point unit, and two integer units
DDR1/DDR2 memory controller supporting a 32/64-bit interface
Peripheral interfaces, such as a 32-bit PCI interface with up to 66-MHz operation
32-bit local bus interface running up to 133-MHz
USB 2.0 (full/high speed) support
Power management controller for low-power consumption
High degree of software compatibility with previous-generation PowerQUICC processor-based
designs for backward compatibility and easier software migration
Optional security engine provides acceleration for control and data plane security protocols
The optional security engine (SEC 3.0) is noted with the extension “E” at the end. It allows CPU-intensive
cryptographic operations to be offloaded from the main CPU core. The security-processing accelerator
provides hardware acceleration for the DES, 3DES, AES, SHA-1, and MD-5 algorithms.
DMA
PCI
MPC8379E
SATA
PHY
DDR1/DDR2
SDRAM
Security
Enhanced
e300 Core
32 KB
I-Cache
32 KB
D-Cache
DUART
Dual I2C
Timers
GPIO
SPI
Interrupt
Controller
RGMII, RMII,
eTSEC
RTBI, MII
Local Bus
USB 2.0
Hi-Speed
Host
Device
RGMII, RMII,
eTSEC
RTBI, MII
SD/MMC
Controller
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