參數(shù)資料
型號: KMPC8378VRALG
廠商: Freescale Semiconductor
文件頁數(shù): 118/128頁
文件大?。?/td> 0K
描述: IC MPU POWERQUICC II 689-PBGA
標(biāo)準(zhǔn)包裝: 2
系列: MPC83xx
處理器類型: 32-位 MPC83xx PowerQUICC II Pro
速度: 667MHz
電壓: 1V
安裝類型: 表面貼裝
封裝/外殼: 689-BBGA 裸露焊盤
供應(yīng)商設(shè)備封裝: 689-TEPBGA II(31x31)
包裝: 托盤
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
Freescale Semiconductor
9
This figure shows the undershoot and overshoot voltages at the interfaces of the device.
Figure 2. Overshoot/Undershoot Voltage for GVDD/LVDD/OVDD/LBVDD
2.1.3
chip
Output Driver Characteristics
This table provides information on the characteristics of the output driver strengths. The values are
preliminary estimates.
Table 4. Output Drive Capability
Driver Type1
Output Impedance (
Ω)
Supply Voltage
Local bus interface utilities signals
45
LBVDD = 2.5 V, 3.3 V
40
LBVDD = 1.8 V
PCI signals
25
OVDD = 3.3 V
DDR1 signal
18
GVDD = 2.5 V
DDR2 signal
18
GVDD = 1.8 V
eTSEC 10/100/1000 signals
45
LVDD = 2.5 V, 3.3 V
DUART, system control, I2C, JTAG, SPI, and USB
45
OVDD = 3.3 V
GPIO signals
45
OVDD = 3.3 V
Note:
1. Specialized SerDes output capabilities are described in the relevant sections of these specifications (such as SGMII and
PCI Express)
GND
GND – 0.3 V
GND – 0.7 V
Not to Exceed 10%
G/L/O/LBVDD + 20%
G/L/O/LBVDD
G/L/O/LBVDD + 5%
of tinterface1
1. Note that tinterface refers to the clock period associated with the bus clock interface.
VIH
VIL
Note:
2. Note that with the PCI overshoot allowed (as specified above), the device does
not fully comply with the maximum AC ratings and device protection guideline outlined in
the
PCI Rev. 2.3 Specification (Section 4.2.2.3).
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