參數(shù)資料
型號: KMPC8360VVALFHA
廠商: Freescale Semiconductor
文件頁數(shù): 45/102頁
文件大?。?/td> 0K
描述: IC MPU POWERQUICC II PRO 740TBGA
標(biāo)準(zhǔn)包裝: 2
系列: MPC83xx
處理器類型: 32-位 MPC83xx PowerQUICC II Pro
速度: 667MHz
電壓: 1.3V
安裝類型: 表面貼裝
封裝/外殼: 740-LBGA
供應(yīng)商設(shè)備封裝: 740-TBGA(37.5x37.5)
包裝: 托盤
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
Freescale Semiconductor
47
I2C DC Electrical Characteristics
This figure provides the test access port timing diagram.
Figure 33. Test Access Port Timing Diagram
11
I2C
This section describes the DC and AC electrical characteristics for the I2C interface of the MPC8360E/58E.
11.1
I2C DC Electrical Characteristics
This table provides the DC electrical characteristics for the I2C interface of the device.
Table 44. I2C DC Electrical Characteristics
At recommended operating conditions with OVDD of 3.3 V ± 10%.
Parameter
Symbol
Min
Max
Unit
Notes
Input high voltage level
VIH
0.7
× OVDD
OVDD + 0.3
V
Input low voltage level
VIL
–0.3
0.3
× OVDD
V—
Low level output voltage
VOL
00.4
V
Output fall time from VIH(min) to VIL(max) with a bus
capacitance from 10 to 400 pF
tI2KLKV
20 + 0.1
× CB
250
ns
Pulse width of spikes which must be suppressed by the input
filter
tI2KHKL
050
ns
Capacitance for each I/O pin
CI
—10
pF
Input current (0 V
≤VIN ≤OVDD)IIN
—±10
μA
Notes:
1. Output voltage (open drain or open collector) condition = 3 mA sink current.
2. CB = capacitance of one bus line in pF.
3. Refer to the MPC8360E Integrated Communications Processor Reference Manual for information on the digital filter used.
4. I/O pins obstruct the SDA and SCL lines if OVDD is switched off.
VM = Midpoint Voltage (OVDD/2)
VM
tJTIVKH
tJTIXKH
JTAG
External Clock
Output Data Valid
tJTKLOX
tJTKLOZ
tJTKLOV
Input
Data Valid
Output Data Valid
TDI, TMS
TDO
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