參數(shù)資料
型號(hào)： KMPC8358ZUAGDGA
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 56/95頁(yè)
文件大?。?/td> 0K
描述： IC MPU POWERQUICC II PRO 740TBGA
標(biāo)準(zhǔn)包裝： 2
系列： MPC83xx
處理器類型： 32-位 MPC83xx PowerQUICC II Pro
速度： 400MHz
電壓： 1.2V
安裝類型： 表面貼裝
封裝/外殼： 740-LBGA
供應(yīng)商設(shè)備封裝： 740-TBGA（37.5x37.5）
包裝： 托盤(pán)
MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3
6
Freescale Semiconductor
Overview
— Data bus widths:
– Single 32-bit data PCI interface that operates at up to 66 MHz
— PCI 3.3-V compatible (not 5-V compatible)
— PCI host bridge capabilities on both interfaces
— PCI agent mode supported on PCI interface
— Support for PCI-to-memory and memory-to-PCI streaming
— Memory prefetching of PCI read accesses and support for delayed read transactions
— Support for posting of processor-to-PCI and PCI-to-memory writes
— On-chip arbitration, supporting five masters on PCI
— Support for accesses to all PCI address spaces
— Parity support
— Selectable hardware-enforced coherency
— Address translation units for address mapping between host and peripheral
— Dual address cycle supported when the device is the target
— Internal configuration registers accessible from PCI
Local bus controller (LBC)
— Multiplexed 32-bit address and data operating at up to 133 MHz
— Eight chip selects support eight external slaves
— Up to eight-beat burst transfers
— 32-, 16-, and 8-bit port sizes are controlled by an on-chip memory controller
— Three protocol engines available on a per chip select basis:
– General-purpose chip select machine (GPCM)
– Three user programmable machines (UPMs)
– Dedicated single data rate SDRAM controller
— Parity support
— Default boot ROM chip select with configurable bus width (8-, 16-, or 32-bit)
Programmable interrupt controller (PIC)
— Functional and programming compatibility with the MPC8260 interrupt controller
— Support for 8 external and 35 internal discrete interrupt sources
— Support for one external (optional) and seven internal machine checkstop interrupt sources
— Programmable highest priority request
— Four groups of interrupts with programmable priority
— External and internal interrupts directed to communication processor
— Redirects interrupts to external INTA pin when in core disable mode
— Unique vector number for each interrupt source
Dual industry-standard I2C interfaces
— Two-wire interface
相關(guān)PDF資料
PDF描述
KMPC8358ZQAGDDA IC MPU POWERQUICC II PRO 668PBGA
KMPC8358VVAGDGA IC MPU POWERQUICC II PRO 740TBGA
1-84982-1 CONN FFC 11POS 1.00MM VERT SMD
2-84534-5 CONN FFC 25POS 1.25MM VERT
1-84534-7 CONN FFC 17POS 1.25MM VERT
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