參數(shù)資料
型號: KMPC8358VVAGDGA
廠商: Freescale Semiconductor
文件頁數(shù): 47/95頁
文件大?。?/td> 0K
描述: IC MPU POWERQUICC II PRO 740TBGA
標準包裝: 2
系列: MPC83xx
處理器類型: 32-位 MPC83xx PowerQUICC II Pro
速度: 400MHz
電壓: 1.2V
安裝類型: 表面貼裝
封裝/外殼: 740-LBGA
供應(yīng)商設(shè)備封裝: 740-TBGA(37.5x37.5)
包裝: 托盤
MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3
Freescale Semiconductor
51
PCI
12 PCI
This section describes the DC and AC electrical specifications for the PCI bus of the MPC8358E.
12.1
PCI DC Electrical Characteristics
Table 45 provides the DC electrical characteristics for the PCI interface of the device.
12.2
PCI AC Electrical Specifications
This section describes the general AC timing parameters of the PCI bus of the device. Note that the
PCI_CLK or PCI_SYNC_IN signal is used as the PCI input clock depending on whether the device is
configured as a host or agent device. Table 46 provides the PCI AC timing specifications at 66 MHz.
.
Table 45. PCI DC Electrical Characteristics
Parameter
Symbol
Test Condition
Min
Max
Unit
High-level input voltage
VIH
VOUT ≥ VOH (min) or
0.5
× OVDD
OVDD + 0.5
V
Low-level input voltage
VIL
VOUT ≤ VOL (max)
-0.5
0.3
× OVDD
V
High-level output voltage
VOH
IOH = –500 μA0.9 × OVDD
—V
Low-level output voltage
VOL
IOL = 1500 μA—
0.1
× OVDD
V
Input current
IIN
0 V
≤ VIN1 ≤ OVDD
—±10
μA
Note:
1. Note that the symbol VIN, in this case, represents the OVIN symbol referenced in Table 1 and Table 2.
Table 46. PCI AC Timing Specifications at 66 MHz
Parameter
Symbol1
Min
Max
Unit
Notes
Clock to output valid
tPCKHOV
—6.0
ns
2
Output hold from clock
tPCKHOX
1—
ns
2
Clock to output high impedance
tPCKHOZ
—14
ns
2, 3
Input setup to clock
tPCIVKH
3.0
ns
2, 4
Input hold from clock
tPCIXKH
0.3
ns
2, 4
Notes:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tPCIVKH symbolizes PCI timing
(PC) with respect to the time the input signals (I) reach the valid state (V) relative to the PCI_SYNC_IN clock, tSYS, reference
(K) going to the high (H) state or setup time. Also, tPCRHFV symbolizes PCI timing (PC) with respect to the time hard reset
(R) went high (H) relative to the frame signal (F) going to the valid (V) state.
2. See the timing measurement conditions in the
PCI 2.2 Local Bus Specifications.
3. For purposes of active/float timing measurements, the Hi-Z or off-state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
4. Input timings are measured at the pin.
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