參數(shù)資料
型號： KMPC8321ECVRAFDC
廠商： Freescale Semiconductor
文件頁數(shù)： 23/82頁
文件大小： 0K
描述： IC MPU 516-PBGA
標準包裝： 2
系列： MPC83xx
處理器類型： 32-位 MPC83xx PowerQUICC II Pro
速度： 333MHz
電壓： 1V
安裝類型： 表面貼裝
封裝/外殼： 516-BBGA
供應商設備封裝： 516-FPBGA（27x27）
包裝： 托盤
MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4
Freescale Semiconductor
3
Overview
NOTE
The QUICC Engine block can also support a UTOPIA level 2 capable of
supporting 31 multi-PHY (MPC8323E- and MPC8323-specific).
The MPC8323E security engine (SEC 2.2) allows CPU-intensive cryptographic operations to be offloaded
from the main CPU core. The security-processing accelerator provides hardware acceleration for the DES,
3DES, AES, SHA-1, and MD-5 algorithms.
In summary, the MPC8323E family provides users with a highly integrated, fully programmable
communications processor. This helps ensure that a low-cost system solution can be quickly developed
and offers flexibility to accommodate new standards and evolving system requirements.
1.1
MPC8323E Features
Major features of the MPC8323E are as follows:
High-performance, low-power, and cost-effective single-chip data-plane/control-plane solution for
ATM or IP/Ethernet packet processing (or both).
MPC8323E QUICC Engine block offers a future-proof solution for next generation designs by
supporting programmable protocol termination and network interface termination to meet evolving
protocol standards.
Single platform architecture supports the convergence of IP packet networks and ATM networks.
DDR1/DDR2 memory controller—one 32-bit interface at up to 266 MHz supporting both DDR1
and DDR2.
An e300c2 core built on Power Architecture technology with 16-Kbyte instruction and data caches,
and dual integer units.
Peripheral interfaces such as 32-bit PCI (2.2) interface up to 66-MHz operation, 16-bit local bus
interface up to 66-MHz operation, and USB 2.0 (full-/low-speed).
Security engine provides acceleration for control and data plane security protocols.
High degree of software compatibility with previous-generation PowerQUICC processor-based
designs for backward compatibility and easier software migration.
1.1.1
Protocols
The protocols are as follows:
ATM SAR up to 155 Mbps (OC-3) full duplex, with ATM traffic shaping (ATF TM4.1)
Support for ATM AAL1 structured and unstructured circuit emulation service (CES 2.0)
Support for IMA and ATM transmission convergence sub-layer
ATM OAM handling features compatible with ITU-T I.610
IP termination support for IPv4 and IPv6 packets including TOS, TTL, and header checksum
processing
Extensive support for ATM statistics and Ethernet RMON/MIB statistics
Support for 64 channels of HDLC/transparent
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KMPC8321ECZQAFDC 功能描述:微處理器 - MPU 8321 PBGA W/ENCR RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324
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