參數(shù)資料
型號(hào): KMPC8315ECVRAGDA
廠商: Freescale Semiconductor
文件頁數(shù): 95/106頁
文件大?。?/td> 0K
描述: IC MPU POWERQUICC II 620-PBGA
標(biāo)準(zhǔn)包裝: 2
系列: MPC83xx
處理器類型: 32-位 MPC83xx PowerQUICC II Pro
速度: 400MHz
電壓: 1V
安裝類型: 表面貼裝
封裝/外殼: 620-BBGA 裸露焊盤
供應(yīng)商設(shè)備封裝: 620-PBGA(29x29)
包裝: 托盤
MPC8315E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
89
Package and Pin Listings
VSS1IO
M24, N24, P19, P20, P25, P27, R25, R27,
T24
I—
XCOREVDD
P2, P10, R2, T1
I
XCOREVSS
R3, R10, U2, V2
I
XPADVDD
P3, R9, U3
I
XPADVSS
P5, P9, V3
I
Note:
1. This pin is an open drain signal. A weak pull-up resistor (1 k
) should be placed on this pin to NVDD.
2. This pin is an open drain signal. A weak pull-up resistor (2–10 k
) should be placed on this pin to NVDD.
3. This output is actively driven during reset rather than being three-stated during reset.
4. These JTAG pins have weak internal pull-up P-FETs that are always enabled.
5. This pin should have a weak pull up if the chip is in PCI host mode. Follow PCI specifications recommendation.
6. This pin must always be tied to VSS.
7. Thermal sensitive resistor.
8. This pin should be
connected to USB_VSSA_BIAS through 10K precision resistor.
9. The LB_POR_CFG_BOOT_ECC functionality for this pin is only available in MPC8315E revision 1.1 and later. The
LB_POR_CFG_BOOT_ECC is sampled only during the PORESET negation. This pin with an internal pull down resistor enables
the ECC by default. To disable the ECC an external strong pull up resistor or a tristate buffer is needed.
10.This pin should be connected to an external 2.7 K ±1% resistor connected to VSS. The resistor should be placed as close as
possible to the input.
11.This pin has a weak internal pull-down.
12.This pin has a weak internal pull-up.
Table 70. MPC8315E TEPBGA II Pinout Listing (continued)
Signal
Package Pin Number
Pin Type
Power
Supply
Note
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