參數(shù)資料
型號: KMPC8315CVRAGDA
廠商: Freescale Semiconductor
文件頁數(shù): 54/106頁
文件大小: 0K
描述: IC MPU POWERQUICC II 620-PBGA
標(biāo)準包裝: 2
系列: MPC83xx
處理器類型: 32-位 MPC83xx PowerQUICC II Pro
速度: 400MHz
電壓: 1V
安裝類型: 表面貼裝
封裝/外殼: 620-BBGA 裸露焊盤
供應(yīng)商設(shè)備封裝: 620-PBGA(29x29)
包裝: 托盤
MPC8315E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
51
High-Speed Serial Interfaces (HSSI)
This figure shows the PCI input AC timing conditions.
Figure 36. PCI Input AC Timing Measurement Conditions
This figure shows the PCI output AC timing conditions.
Figure 37. PCI Output AC Timing Measurement Condition
15 High-Speed Serial Interfaces (HSSI)
This section describes the common portion of SerDes DC electrical specifications, which is the DC
requirement for SerDes Reference Clocks. The SerDes data lane’s transmitter and receiver reference
circuits are also shown.
15.1
Signal Terms Definition
The SerDes utilizes differential signaling to transfer data across the serial link. This section defines terms
used in the description and specification of differential signals.
Figure 38 shows how the signals are defined. For illustration purpose, only one SerDes lane is used for
description. The figure shows waveform for either a transmitter output (TXn and TXn) or a receiver input
(RXn and RXn). Each signal swings between A Volts and B Volts where A > B.
Using this waveform, the definitions are as follows. To simplify illustration, the following definitions
assume that the SerDes transmitter and receiver operate in a fully symmetrical differential signaling
environment.
1. Single-Ended Swing
The transmitter output signals and the receiver input signals TXn, TXn, RXn and RXn each have
a peak-to-peak swing of A – B Volts. This is also referred as each signal wire’s Single-Ended
Swing.
2. Differential Output Voltage, VOD (or Differential Output Swing):
tPCIVKH
CLK
Input
tPCIXKH
CLK
Output Delay
tPCKHOV
High-Impedance
tPCKHOZ
Output
tPCKHOX
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